Bus Synchronizer for Distributed Control Clock Drift
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Solution Overview
Problem
In distributed control systems, data collisions occur due to clock drift among I/O modules and controllers, leading to inefficiencies and safety concerns in explosive-atmosphere environments, where existing solutions require expensive hardware upgrades and are not field-upgradeable.
Innovation Solution
A bus synchronizer generates synchronization pulses to reset CPU timers and slot counters of I/O modules, synchronizing them with a real-time clock to mitigate clock drift and prevent data collisions, using a variable-rate TDMA data bus that conserves power and allows for flexible data rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock synchronization is implemented using existing hardware solutions, then data collision prevention is improved, but system cost increases and field-upgradeability is reduced
Solution Approach 1:
The patent uses software-based synchronization that copies the functionality of expensive hardware synchronization solutions. The master controller generates synchronization pulses and distributes them to I/O modules via the existing data bus, replicating the effect of dedicated hardware synchronization circuits without requiring physical hardware changes or upgrades.
Solution Approach 2:
The patent replaces mechanical/hardware-based clock synchronization mechanisms with an electronic/software-based approach. Instead of using physical clock distribution circuits or dedicated synchronization hardware, the system uses software-controlled pulse generation and timing mechanisms that operate through the existing data bus infrastructure.
2Measurement precision
If fixed data rate is used for synchronization, then timing precision is improved, but power consumption increases
Solution Approach 1:
The patent implements a dynamic data rate adjustment mechanism where the synchronization pulse frequency is varied based on the actual timing requirements of the system. The master controller can adjust the data rate between pulses, using higher rates when precise timing is needed and lower rates during intervals where less precision is required, thereby optimizing power consumption while maintaining necessary timing precision.
Solution Approach 2:
The system changes the operational parameters of the data bus dynamically, adjusting the data rate according to the synchronization needs. By varying parameters such as pulse frequency and data transmission rate, the system achieves precise timing when necessary while reducing power consumption during periods of lower precision requirements.
Data Source
AI summary
Methods, apparatus, systems, and articles of manufacture are disclosed to synchronize data bus access. An example system includes a first computing device to transmit a first synchronization pulse to second computing devices using a first bus, the first synchronization pulse to synchronize first timers of the second computing devices to trigger a data schedule including one or more data cycles, and transmit a second synchronization pulse to the second computing devices using the first bus, the second synchronization pulse to synchronize ones of the first timers and slot counters of the second computing devices to trigger the one or more data cycles. The example system further includes the second computing devices to transmit data to the first computing device using a second bus during the one or more data cycles, where each of the one or more data cycles is assigned to a corresponding one of the second computing devices.