Bus System Clock Synchronization via Monotone Clock Mediator
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Solution Overview
Problem
Existing bus systems face challenges in synchronizing slave system clocks with master system clocks across multiple components in a clock-synchronous communication system, leading to inaccuracies and drift errors, especially in decentralized setups where direct access to a central time server is limited.
Innovation Solution
A bus system architecture where a master component with a master system clock synchronizes slave components using a synchronization command transmitted in parallel, allowing each slave to calculate its system time based on the synchronization time, synchronization signal time, and current monotone clock time, with optional compensation for drift errors, enabling precise timekeeping without direct access to a central time server.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a reference clock is used to cyclically determine local error and regulate clock speed, then clock synchronization accuracy is improved, but system complexity and drift error accumulation worsen
Solution Approach 1:
The patent introduces a monotone clock as an intermediary time base that runs continuously without regulation. This monotone clock serves as a mediator between the regulated system clock and the synchronization process, eliminating the need for continuous error determination and clock speed regulation. The monotone clock simply provides a stable reference that accumulates time linearly, while the system clock is adjusted to match it, thereby reducing system complexity while maintaining synchronization accuracy.
Solution Approach 2:
The patent extracts the timekeeping function from the regulated clock system and places it in a separate monotone clock. By separating the time base generation (monotone clock) from the time regulation (system clock adjustment), the system eliminates the need for continuous feedback loops and error calculations, thereby reducing complexity while preserving synchronization precision.
2Measurement precision
If continuous resynchronization is performed to maintain clock-synchronous data exchange, then synchronization accuracy is improved, but communication overhead and processing time worsen
Solution Approach 1:
The patent implements periodic synchronization events where the master component sends synchronization commands at regular intervals rather than continuously adjusting clocks. This periodic approach allows the system to maintain synchronization accuracy while reducing the processing time and communication overhead associated with continuous resynchronization. The monotone clock ensures that between synchronization events, time can be calculated directly without intervention.
3Measurement precision
If slave components directly access a central time server, then time synchronization accuracy is improved, but system architecture complexity and communication requirements worsen
Solution Approach 1:
The master component acts as an intermediary between the external time source and the slave components. Instead of each slave directly accessing the central time server, the master receives time information and distributes it to slaves via synchronization commands. This intermediary approach simplifies the system architecture by centralizing time management while maintaining synchronization accuracy across all components.
Solution Approach 2:
Each slave component maintains its own monotone clock that independently tracks time without requiring direct access to external time servers. The slaves self-synchronize by comparing their monotone clock time with synchronization commands from the master, thereby reducing communication requirements and architectural complexity while maintaining time synchronization accuracy.
Data Source
AI summary
A bus system having a plurality of bus components connected in a bus for the transmission of process data by all bus components, with a master as one of the bus components, with at least one slave as one of the bus components. The master has a master system clock for a master system time. The slave has a slave system clock for a slave system time to be synchronized with the master system time. The master is set up to send a synchronization command at a synchronization time via the bus for the parallel reception by the bus components embodied as slaves. The slave system clock of the slave is set up to calculate and output the slave system time based on the synchronization time received by the data transmission and the synchronization signal time and the current time value of the monotone clock.