Simulation Bus Trace Capture Using State-Machine Error Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current logic simulators face challenges in efficiently decoding bus traces, particularly in layered bus designs, where identifying the start of a data packet is ambiguous, leading to computational resource wastage and limited practicality in capturing full simulation ranges.
Innovation Solution
The system generates additional logic to monitor and track signals within the logic design, using a state-machine to identify data packet starts and differentiate between control and raw data packets, allowing for accurate decoding and efficient bus trace capture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If logic simulators capture full simulation ranges to ensure complete debugging coverage, then debugging comprehensiveness is improved, but computational resource consumption increases significantly
Solution Approach 1:
The patent extracts and captures only the relevant portion of bus traces that contain actual error information, rather than capturing the entire simulation range. The system identifies and isolates specific time windows where errors occur, extracting only those portions for detailed analysis, thereby reducing computational resource consumption while maintaining debugging comprehensiveness.
Solution Approach 2:
The patent applies partial action by capturing bus traces selectively based on error detection signals rather than continuously capturing all simulation data. When no errors are detected, the system skips trace capture or captures only minimal information, performing the debugging action partially rather than excessively across the entire simulation range.
2Measurement precision
If logic simulators capture detailed bus traces to improve error detection accuracy, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent performs preliminary error detection by monitoring logic under test before attempting detailed bus trace capture. The system first executes a preliminary check to determine if errors are present, and only then proceeds to capture detailed traces. This preliminary action prevents unnecessary complex trace capture operations when no errors exist, reducing overall system complexity while maintaining error detection precision.
Solution Approach 2:
The patent introduces an intermediary error detection mechanism that sits between the logic under test and the bus trace capture system. This intermediary layer analyzes logic outputs and only triggers detailed trace capture when errors are detected, acting as a mediator that simplifies the overall system by preventing direct, continuous trace capture while maintaining high error detection accuracy.
3Loss of information
If logic simulators attempt to decode all bus traces to ensure complete analysis, then information completeness is improved, but processing time increases
Solution Approach 1:
The patent extracts only the essential error-related information from bus traces rather than decoding all trace data. When errors are detected, the system extracts specific signal values and timing information relevant to the error, discarding redundant data. This extraction approach maintains information completeness for debugging while significantly reducing processing time.
Solution Approach 2:
The patent applies partial decoding by selectively processing bus trace data based on error detection results. Instead of decoding all traces completely, the system performs partial decoding only on portions containing errors, using intelligent sampling and selective analysis to maintain information completeness while minimizing processing time through targeted rather than exhaustive decoding.
Data Source
AI summary
Provided are systems, methods, and media for handling simulation of logic under test. An example method includes receiving a simulation model for the logic under test. Generating second logic that is configured to create a set of output logic signals based on an existing set of input logic signals of the logic under test. Rebuilding the simulation model based, at least in part, on the second logic. Examining a netlist of the rebuilt simulation model to identify the set of output logic signals created by the second logic. Generating during the execution of the simulation, a bus trace that is configured to capture at least the identified set of output logic signals.