Out-of-order Bus Transaction Execution via Hardware Linked Lists
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Solution Overview
Problem
Existing designs for on-chip bus protocols, such as multi-layer AXI, require large and power-hungry control logic to manage a mixture of in-order and out-of-order transactions and data interleaving, necessitating a more efficient and low-power implementation.
Innovation Solution
The system employs hardware linked lists to store and manage in-order transactions and interleaved data, with control circuitry selecting transactions for execution based on dependencies, using address and data buffers, and additional components like arbitration units and burst shapers to optimize transaction ordering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If FIFO buffers and simple buffers are used to capture bus transactions, then the implementation is small and simple, but sophisticated control logic is required to manage in-order and out-of-order transactions and data de-interleaving, making the design large and power-hungry
Solution Approach 1:
Instead of using simple FIFO buffers with complex control logic to manage transaction ordering, the patent inverts the approach by using sophisticated buffered logic that inherently tracks and manages transaction dependencies. This buffered logic stores not just data but also metadata about transaction origins, destinations, and ordering requirements, allowing the system to naturally handle out-of-order execution without requiring additional complex control mechanisms.
Solution Approach 2:
The patent introduces buffered logic as an intermediary layer between the FIFO buffers and the transaction execution mechanism. This buffered logic acts as a mediator that receives transactions from multiple masters, tracks their dependencies, determines proper execution order, and releases transactions to the execution unit. By placing this intelligent intermediary, the system achieves efficient out-of-order execution without requiring each buffer to implement complex control logic.
2Productivity
If out-of-order execution is implemented to increase throughput, then fast transactions can execute sooner, but complex control logic is needed to manage transaction dependencies and ordering
Solution Approach 1:
The patent applies preliminary action by pre-tracking transaction dependencies and ordering requirements when transactions are first received and stored in the buffers. The buffered logic records metadata about each transaction's master, destination, and position in the original sequence before execution begins. This preliminary tracking eliminates the need for complex real-time control logic during execution, as the ordering information is already captured and can be used to efficiently determine execution order.
Solution Approach 2:
The patent replaces mechanical control logic with a more elegant buffered logic system that uses stored transaction metadata to determine execution order. Instead of using complex control circuits to actively manage and arbitrate between transactions in real-time, the system substitutes this with a buffered approach where transaction information is stored with its dependency context, and execution order emerges naturally from this stored information without requiring active mechanical control.
3Device complexity
If transactions are executed in-order to maintain simplicity, then control logic is simpler, but fast transactions are delayed by slow transactions reducing overall throughput
Solution Approach 1:
The patent introduces dynamics by allowing the transaction execution order to be flexible rather than fixed. The buffered logic dynamically determines execution order based on the current state of buffered transactions and their dependencies. When a fast transaction becomes available and its dependencies are satisfied, it can be executed immediately even if slower transactions are still being processed. This dynamic approach maximizes throughput while keeping control logic manageable through the use of pre-stored transaction metadata.
Data Source
AI summary
A slave-interface unit for use with a system-on-a-chip bus (such as an AXI bus) executes received transactions out-of-order while accounting for groups of in-order transactions.