Bus Transfer Control via Authorization Signal Chain
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Solution Overview
Problem
Existing systems for transferring information from electronic components to a host device through a communication bus suffer from inefficiencies, including non-systematic data sequencing and additional synchronization delays, which slow down read speed, especially when dealing with faulty components and synchronous receiving hosts.
Innovation Solution
A device comprising a chain of processing blocks that propagates an authorization signal and coordinates processing with an independent clock signal, allowing for systematic and sequential data transfer without the need for additional synchronization with the host clock, thereby enhancing read speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If time-multiplexing with asynchronous handshake protocol is used, then faulty components can be handled, but read speed is reduced due to non-systematic sequencing and synchronization delays
Solution Approach 1:
The patent implements clock-multiplexed sequential access where each electronic component is assigned a specific time slot in a periodic cycle. The host device systematically accesses components in sequence (e.g., component 0, then component 1, etc.) according to a fixed clock schedule, ensuring periodic, predictable access patterns that maintain high read speed while handling faulty components through systematic skipping.
Solution Approach 2:
The host device performs preliminary determination of which electronic components contain valid information before initiating data transfer. By pre-identifying components with data to be read, the system can systematically skip faulty or empty components in advance, avoiding unnecessary access attempts and maintaining optimal read speed through proactive filtering.
2Adaptability or versatility
If additional synchronization step is introduced to synchronize bus multiplexing clock with receiving host clock, then synchronous communication is achieved, but read speed drastically slows down due to additional host clock periods
Solution Approach 1:
The host device independently determines which electronic components contain information and autonomously skips faulty or empty components during the sequential access process. This self-service mechanism eliminates the need for complex synchronization handshaking with individual components, as the host independently manages the access sequence according to its own clock, achieving synchronous communication without speed-penalizing synchronization steps.
Solution Approach 2:
The system uses a fixed clock-multiplexed schedule where the host device systematically accesses components in predetermined time slots. This periodic access pattern naturally synchronizes with the host's internal clock without requiring additional synchronization protocols, as the access rhythm is inherently tied to the host's clock cycles from the outset.
3Ease of operation
If systematic sequential reading is implemented, then fair bus access is ensured, but additional synchronization delays occur when communicating with synchronous receiving hosts
Solution Approach 1:
The patent implements a clock-multiplexed system where bus access is systematically allocated to each electronic component in fixed periodic time slots. This ensures fair, predictable access for all components while the periodic nature of the access pattern naturally aligns with the host's clock cycles, eliminating the need for additional synchronization delays that would occur with aperiodic or event-driven access schemes.
Data Source
AI summary
A device for controlling a transfer of information from a plurality of electronic components through a communication bus to a host device, comprising a chain of processing blocks connected to the electronic components, each of the processing blocks associated with one, or a set, of the electronic components, which processing blocks are arranged such that during the transfer of information an authorization signal propagates through the chain of processing blocks and, when the authorization signal encounters a processing block associated with one of the electronic components or one of the sets of electronic components which contains an information value to be transferred, effecting the transfer of the information value through the communication bus to the host device. The processing blocks are arranged to coordinate their processing in accordance with a clock signal generated independent of a propagation status of the authorization signal within the chain of processing blocks.