Buss-less Semiconductor Substrate with Selective Metallization
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Solution Overview
Problem
Conventional electroplating techniques for semiconductor packages require bus and tie bars, leading to limited substrate space for signal traces, compromised trace pitch due to enlarged trace volume, and reduced adhesion of plated traces to encapsulating compounds, resulting in reliability hazards and increased costs.
Innovation Solution
A substrate-wide seed layer is used to distribute plating potential, allowing electroplating of copper traces with specific aspect ratios and thin nickel/gold layers, while keeping sidewalls uncoated to enhance adhesion and eliminate the need for bus bars, thereby optimizing substrate space and reducing precious metal usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If electroplating technique is used to deposit metal layers on substrate traces, then metallurgical affinity for gold and solder attachment is achieved, but substrate real estate is consumed by bus and tie bars limiting signal trace placement
Solution Approach 1:
The patent removes the bus and tie bars from the substrate structure entirely. Instead of using these traditional current distribution elements, the invention uses the substrate ground plane itself as the current return path and distributes plating current through the substrate ground plane and via structures, eliminating the need for dedicated bus and tie bar structures that consume valuable substrate area.
Solution Approach 2:
The substrate ground plane serves multiple functions: it acts as the electrical ground reference, provides current return paths, and serves as the current distribution network for electroplating operations. This multi-functional approach eliminates the need for separate bus and tie bar structures, maximizing the area available for signal traces.
2Reliability
If electroplating deposits layers on all metallic surfaces including sides of traces, then metallurgical affinity is achieved, but trace volume increases compromising trace pitch
Solution Approach 1:
The patent applies metallization selectively to specific surfaces of the traces. The top surface of the traces receives the full multi-layer metallization (electroless copper, electroplated copper, nickel, and gold) for optimal solder attachment. The sidewalls receive only a thin electroless copper layer or no metallization at all, preventing excessive volume increase while maintaining necessary metallurgical properties at the critical bonding interface.
Solution Approach 2:
Instead of applying complete metallization uniformly to all trace surfaces, the patent applies metallization partially - specifically targeting the top surface where solder attachment is critical. This partial metallization approach provides sufficient metallurgical affinity for reliable solder bonding while minimizing the volume increase that would compromise trace pitch and signal integrity.
3Ease of manufacture
If bus and tie bars are cut in final assembly, then device extraction from substrate strip is enabled, but exposed copper edges corrode reducing reliability
Solution Approach 1:
The patent removes the bus and tie bar structures that cause corrosion problems. By eliminating these separate current distribution elements, there are no cut edges exposed to the environment that could corrode. The current distribution function is transferred to the substrate ground plane, which remains intact and does not require cutting.
Solution Approach 2:
The patent uses a composite metallization structure with multiple layers (electroless copper, electroplated copper, nickel, and gold) where the outer gold and nickel layers provide corrosion protection to the underlying copper traces. This protective layering prevents corrosion at trace edges without requiring bus and tie bar structures.
4Reliability
If conventional technology adds more metal layers to substrate, then adhesion to epoxy-based molding compounds is improved, but substrate cost increases by 10% to 30%
Solution Approach 1:
The patent eliminates the need for additional expensive metal layers and conductive vias by using the substrate ground plane and via structures as the current distribution network. This approach achieves the necessary electrical functionality and adhesion properties without adding the 10% to 30% cost increase associated with multiple metal layers and via interconnections.
Solution Approach 2:
The substrate structure itself serves the dual purpose of current distribution and adhesion enhancement. The ground plane and via structures provide both electrical functionality and mechanical anchoring for the molding compound, eliminating the need for separate expensive metal layers and via interconnections that would otherwise be required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables denser trace layouts, improved adhesion to encapsulation compounds, and cost savings by eliminating the need for bus bars and reducing precious metal usage, while maintaining low electrical resistance and trace fatigue.
Implementation Method 1
electrolytically plating the traces (about 18 μm copper) on the exposed seed layer
Implementation Method 2
by keeping the resist on the trace sides as shields to restrict the deposition of additional layers to the trace tops
Implementation Method 3
the anisotropic etching of the seed layer creates an etch undercut, which offers an additional lock for the polymerized encapsulation compound, thus enhancing the compound adhesion
Data Source
AI summary
A ball grid array device with an insulating substrate (110) having metal traces (106, for example copper, about 18 μm thick) with sidewalls (108) at right angles to the trace top. The traces are grouped in a first (120) and a second set (121). The first set traces have the top surface covered by a thin noble metal (for example a nickel layer (130) about 0.1 μm thick and an outermost gold layer (131) about 0.5 μm thick), while the sidewalls are un-covered by the noble metal. About 1.5 μm are thus gained for the trace spacing; oxidation of the trace sidewalls is enabled. The second set traces have the top surface un-covered by the noble metal; the traces are covered by an insulating soldermask. A semiconductor chip (101) with terminals (102) is attached to the substrate with the terminals connected to the noble metal of the first set traces, either by bonding wires (for example gold) or by metal studs (for example gold). The assembled chip and the first set traces are encapsulated in a polymerized compound (160), which adheres to the oxidized trace sidewalls and locks into the trace undercuts at the substrate interface.