Four-Side Buttable X-Ray Detector Readout Architecture
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional back-side illuminated (BSI) imagers require a large number of sub-imagers for X-ray detection, leading to a significant amount of digital input/output control lines and massive parallel data processing, which complicates address and readout data management for fast frame rates in medical diagnostic equipment.
Innovation Solution
A four-side buttable CMOS imager with on-wafer distributed readout electronics, including a programmable logic device like a CPLD, and shared analog front ends with multiple amplifiers and ADCs, allowing for scalable and addressable control and readout architecture, reducing the need for external ROM and optimizing data processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a large number of sub-imagers are used to achieve fast frame rates, then productivity is improved, but device complexity increases due to complex digital input/output control and massive parallel data processing requirements
Solution Approach 1:
The detector is divided into multiple sub-imagers that can be butted together to form a complete detector array. Each sub-imager contains its own integrated readout electronics and programmable logic device, allowing independent operation and reducing the complexity of centralized control for the entire system.
Solution Approach 2:
The patent transitions from conventional planar architecture to a three-dimensional stacked architecture where photodiodes, readout electronics, and programmable logic devices are vertically integrated on the same substrate. This 3D integration reduces the physical footprint and interconnection complexity while maintaining high frame rate capability.
2Ease of manufacture
If conventional BSI imager architecture is used with separate photodiode and circuitry layers, then manufacturing is simplified, but device complexity increases due to multiple layers of chips stacked in 3D package requiring extensive interconnections
Solution Approach 1:
The patent combines photodiodes, readout electronics, and programmable logic devices into a single integrated CMOS substrate. This merger eliminates the need for separate photodiode layers and multiple chip stacking, simplifying both manufacturing and reducing interconnection complexity while maintaining the benefits of BSI architecture.
3Measurement precision
If hundreds of sub-imagers are used to obtain complete image coverage, then measurement precision is improved, but loss of time increases due to extensive address and control lines required for readout
Solution Approach 1:
Each sub-imager contains integrated readout electronics and programmable logic devices that are pre-configured on the substrate. This preliminary integration allows parallel readout operations across multiple sub-imagers, eliminating the sequential addressing delays that would occur with centralized control and reducing overall readout time while maintaining high resolution coverage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables efficient data processing and reduced noise by allowing selective binning at the analog level, achieving high-resolution images within the region of interest while minimizing data acquisition outside the ROI, thus improving frame rate and image quality.
Implementation Method 1
imaging sensor array 110 with pixels containing photodiodes that are exposed to incident light
Data Source
Figure 1
Figure 2
Figure 3
AI summary
An imager tile including four-side buttable sub-imager pixel arrays with on-chip digitizing electronic readout circuit. Pixel groupings formed from among the plurality of imagers. Readout electronics including a buffer amplifier for each of the pixel groupings are connected to respective outputs of buttable imagers. Shared analog front ends connect to respective buffer amplifiers of pixel groupings. An analog-to-digital converter at a common centroid location relative to the shared analog front ends includes three data lines - selection input/output line to individually select an output, a clock input line, and a shared digital output line. A pixel output from a respective buffer amplifier is addressable by data provided on the selection input/output line, and the pixel output is provided on the shared digital output line. The I/O lines connected to a programmable logic device where the imager serial data input is output as a massively parallel data stream.