Butterfly Computing Buffer Scheduling for Lower Memory Bandwidth
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Solution Overview
Problem
The butterfly process in computing devices requires significant memory bandwidth due to the need for simultaneous reading and writing of two data elements per cycle, which increases hardware cost and power consumption, especially in hardware implementations of number-theoretic transforms like NTT.
Innovation Solution
A computing device with a first and second buffer, a fetch unit, and an arithmetic unit, utilizing a control unit to read and write data in alternating cycles to maintain high hardware utilization while reducing memory bandwidth, by using ping-pong buffering to store and process input data in stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the butterfly process reads and writes two data elements simultaneously per cycle, then the computational speed is improved, but the memory bandwidth requirement increases
Solution Approach 1:
The patent divides the input data into two separate groups (first group and second group), each processed through dedicated buffer paths. This segmentation allows the system to process data in parallel streams, maintaining high computational throughput while distributing memory access loads across different time cycles, thereby reducing peak bandwidth requirements.
Solution Approach 2:
The patent implements alternating read/write cycles where the fetch unit reads the first group of input data in one cycle and writes the first group of updated data in a subsequent cycle, while doing the same for the second group. This periodic action pattern ensures that memory bandwidth is utilized efficiently over time without requiring excessive simultaneous bandwidth.
2Productivity
If more memory bandwidth is allocated for the butterfly process, then the hardware utilization is improved, but the hardware cost and power consumption increase
Solution Approach 1:
The patent employs dynamic buffer management where the first and second buffers alternately serve as input and output buffers across different cycles. This dynamic switching allows the same physical buffer resources to be reused for multiple purposes, maintaining high hardware utilization without requiring additional static memory resources that would increase power consumption.
Solution Approach 2:
The patent recovers and reuses buffer resources by writing updated data back to the original input buffers after processing. The first buffer receives input data, is processed, and then the updated data is written back to the same buffer, which can then be reused for the next batch of input data. This recovery and reuse mechanism maximizes hardware utilization while minimizing the need for additional memory resources.
Data Source
AI summary
The present application discloses a computing device. The computing device is able to perform a butterfly process upon a sequence of 2N input data. The computing device includes a first buffer, a second buffer, a fetch unit, an arithmetic unit, and a control unit. The control unit is configured to have the fetch unit read 2h input data from a memory as a first group of input data to the first buffer, have the arithmetic unit perform h stages of the butterfly process upon the first group of input data to generate a first group of updated data, have the fetch unit read another 2h input data from the memory as a second group of input data to the second buffer when generating the first group of updated data, and have the fetch unit write the first group of updated data to the memory.