Butterfly Network Data Alignment With Precalculated Control Logic
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Solution Overview
Problem
Modern digital signal processors face challenges with increasing workloads, memory bandwidth limitations, and scheduling issues, particularly in real-time data processing, where memory access and data transformation are complex and error-prone due to the growing size and complexity of systems on a chip and the unreliability of smaller transistors and memory registers.
Innovation Solution
A digital data processor with a streaming engine that retrieves a stream of instruction-specified data elements for processing, utilizing a multilayer butterfly network to transform and align data streams, with precalculated control signals generated using simple combinatorial logic, allowing for efficient data transformations while reducing the complexity of multiplexor control circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a multilayer butterfly network is used to transform and align data streams, then data transformation capability is improved, but device complexity increases due to multiple multiplexors and control circuits
Solution Approach 1:
The patent pre-calculates control signals for the butterfly network using simple combinatorial logic before data transformation occurs. This preliminary computation of control signals simplifies the control circuitry while maintaining the ability to perform multiple data transformations through the multilayer butterfly network structure.
2Productivity
If memory access resources are increased to handle real-time data processing, then memory bandwidth is improved, but device complexity and cost increase
Solution Approach 1:
The patent divides the memory access function into two segments: a streaming engine that handles automated address generation and data loading, and a butterfly network that handles data transformation. This segmentation allows efficient memory bandwidth utilization without requiring complex unified memory access resources for both functions.
Solution Approach 2:
The streaming engine automatically generates addresses and loads data without requiring complex control logic in the memory access resources. This self-service capability of the streaming engine reduces the complexity burden on memory access resources while maintaining high memory bandwidth for real-time data processing.
3Volume of moving object
If the number of transistors is reduced to shrink system size, then system size is decreased, but reliability deteriorates due to smaller transistor and memory register unreliability
Solution Approach 1:
The patent introduces a streaming engine as an intermediary layer between memory and the butterfly network. This intermediary handles data movement and transformation with automated control, reducing the need for complex control logic and larger memory structures, thereby enabling system size reduction while maintaining reliability through simplified, more controllable architecture.
4Productivity
If scalar operations are minimized for efficient real-time processing, then processing throughput is improved, but ease of operation decreases due to automated address generation requirements
Solution Approach 1:
The patent replaces manual scalar address generation operations with an automated streaming engine that uses combinatorial logic to generate addresses. This substitution eliminates the need for complex scalar operations while the pre-calculated control signals make the automated system easy to operate, thereby improving throughput without sacrificing ease of operation.
Data Source
AI summary
A method is shown that is operable to transform and align a plurality of fields from an input to an output data stream using a multilayer butterfly or inverse butterfly network. Many transformations are possible with such a network which may include separate control of each multiplexer. This invention supports a limited set of multiplexer control signals, which enables a similarly limited set of data transformations. This limited capability is offset by the reduced complexity of the multiplexor control circuits.