Reconfigurable Butterfly Unit Verification in DSP Chips
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Solution Overview
Problem
Existing methods for verifying operation results in data operations, such as in aerospace, require significant hardware resources or time, leading to high implementation costs and inability to meet timeliness requirements.
Innovation Solution
A fast verification system utilizing a reconfigurable butterfly unit in a DSP chip, which can be configured into different modes for data verification, reducing resource and time overheads by calculating verification values during idle phases and comparing them with a predetermined coefficient.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If spatial modular redundancy manner is used to verify operation results, then verification reliability is improved, but hardware resource overhead increases significantly
Solution Approach 1:
The butterfly unit is designed to perform multiple functions: normal transform operations and verification operations. By reconfiguring the same hardware resources to calculate both operation results and verification values, the system achieves verification reliability without duplicating hardware, thus resolving the contradiction between reliability and hardware resource overhead
Solution Approach 2:
The system uses its own butterfly unit to verify its own operation results by calculating verification values from input data and comparing them with actual output data. This self-verification mechanism improves reliability without requiring external verification hardware, reducing hardware resource overhead
2Quantity of substance
If sequential verification of operation results is performed using same hardware, then hardware resource consumption is reduced, but time overhead increases significantly
Solution Approach 1:
The butterfly unit performs verification calculations during idle phases without interrupting normal operations. By continuously utilizing available time slots to calculate verification values and compare results, the system reduces time overhead while using the same hardware resources, resolving the contradiction between hardware resource consumption and time overhead
3Measurement precision
If hardware duplication is used for verification, then verification accuracy is improved, but device complexity increases
Solution Approach 1:
The same butterfly unit is reconfigured to serve dual purposes: performing transform operations and performing verification calculations. This multi-functionality approach achieves verification accuracy through the same hardware performing different computational tasks, avoiding the need for duplicated verification hardware and thus reducing device complexity
Data Source
AI summary
The present application discloses a verification system and method for an operation result based on a reconfigurable butterfly unit. The system is applicable to a digital signal processing (DSP) chip. The DSP chip includes a reconfigurable butterfly unit. The reconfigurable butterfly unit may be reconfigured into two modes: a first verification mode and a second verification mode. The system includes: a controller, a memory, a verification unit, a first data gating unit, and a second data gating unit. The technical solution in the present application is used to overcome the disadvantage that an existing verification system and an existing verification method consume large hardware resources, thereby reducing the implementation costs of operation result verification.