Buttressed Field Target Design for High NA Lithography Alignment
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Solution Overview
Problem
In semiconductor device manufacturing, aligning IC estates on a wafer without initial markings or landmarks is challenging, leading to increased setup time and reduced efficiency in imaging multiple ICs, particularly due to the lack of clear orientation between adjacent ICs.
Innovation Solution
The use of buttressed markings in the frame region of the photoresist layer, formed by overlapping exposures of adjacent IC fields, allows for the determination of spatial symmetry between first and second portions of individual markings, enabling precise alignment and reducing overlay budgets through improved field shape control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional markings are used in the frame region for alignment, then orientation determination between adjacent IC estates is enabled, but the markings lack sufficient precision for high NA lithography field shape matching
Solution Approach 1:
The marking is divided into two distinct portions: a first portion formed in the first IC estate field and a second portion formed in the second IC estate field. This segmentation allows each portion to be independently formed with high precision by the lithography system, and their relative positions provide precise measurement data for field shape matching and reticle stitching in high NA lithography applications.
Solution Approach 2:
The marking acts as an intermediary element between adjacent IC estates, providing a reference structure that enables precise measurement and alignment. The marking's two portions serve as mediators that capture the relative positioning and field shape information, allowing the auto-alignment system to determine orientations with the precision required for high NA lithography.
2Productivity
If multiple IC estates are imaged sequentially without pre-formed markings, then manufacturing flexibility is maintained, but setup time increases and imaging efficiency decreases
Solution Approach 1:
The marking is formed as a preliminary structure during the lithography process itself, rather than requiring separate pre-marking steps. The first and second portions of the marking are created during normal IC estate imaging, and the auto-alignment system subsequently uses these pre-formed portions for rapid orientation determination, reducing setup time for subsequent IC estates without sacrificing manufacturing flexibility.
3Ease of manufacture
If the marking structure is simplified for ease of manufacture, then production cost decreases, but the marking fails to provide sufficient information for precise orientation determination
Solution Approach 1:
The marking structure serves multiple functions: it acts as both a formation target during lithography and a measurement reference for auto-alignment. The two-port ion design provides universal applicability across different IC estate configurations while maintaining ease of manufacture through standard lithography processes, and simultaneously delivers the precision needed for orientation determination in high NA lithography.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the alignment of IC estates, reduces setup time, and improves overlay control by allowing for more precise field shape matching across various scanner tools, thereby increasing manufacturing efficiency and accuracy.
Implementation Method 1
A photosensitive material (also denoted as photoresist) is deposited on a wafer, and the mask is positioned over the wafer and bright light, e.g. ultraviolet radiation, exposes the photoresist through the mask. Exposure to the light causes sections of the resist to either harden or soften
Implementation Method 2
The light source 102 may include further components (not illustrated), e.g. one or more lens, one or more grating, one or more mirrors, and one or more optical filter
Data Source
AI summary
An apparatus of manufacturing a semiconductor device is provided. The apparatus including a controller configured to: expose a first region of a photoresist layer with a light pattern, expose a second region of the photoresist layer with at least in part the same light pattern, wherein the second region and the first region overlap in an overlap region of the photoresist layer, and wherein light pattern is configured to form, in exposing the first region, a first portion of individual markings in the overlap region of the photoresist layer, and to form, in exposing the second region, a second portion of individual markings in the overlap region of the photoresist layer. By measuring the composite pattern formed in photoresist by overlapping the first exposure with the second exposure, the relative position of the two exposures can be determined and controlled.