BVH Bounding Box Merging for Faster Ray Tracing Traversal

The patent segments the BVH traversal process into distinct hardware-accelerated stages: bounding box merging, node traversal, and intersection testing. Each stage is handled by specialized hardware units that operate in parallel, dividing the computationally intensive ray tracing task into manageable segments that can be processed simultaneously, thereby improving throughput while reducing per-operation resource consumption.

The patent replaces traditional software-based BVH traversal and intersection algorithms with dedicated hardware logic circuits. The bounding box merging unit, traversal unit, and intersection unit are implemented as hardware components that perform computations through electronic logic operations rather than sequential software instructions, dramatically reducing computational overhead and enabling real-time ray tracing performance.

The patent performs preliminary bounding box merging operations that pre-compute and store merged bounding volumes at each BVH node before actual ray traversal begins. This preliminary action creates an optimized hierarchical structure that enables faster traversal by eliminating redundant intersection tests, thereby maintaining accuracy while reducing the time required for detailed ray-scene intersection computations.

The patent implements dynamic traversal strategies where the hardware logic adaptively adjusts the level of detail examined during BVH traversal based on ray direction, scene geometry, and intersection probability. The system dynamically prunes unlikely traversal paths and focuses computational effort on promising regions, maintaining high intersection accuracy while minimizing computation time for real-time rendering.