BVNAND Bonded Structure Without SSL/GSL Cut Regions
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Solution Overview
Problem
Conventional semiconductor device manufacturing methods for bit vector NAND (BVNAND) structures are complex and costly due to the need for forming string select line (SSL) and ground select line (GSL) cut regions, which increases process complexity and cost.
Innovation Solution
The method omits forming SSL and GSL cut regions by creating separation insulating patterns after bonding semiconductor structures, allowing for improved integration and electrical characteristics with reduced process difficulty and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SSL-cut region and GSL-cut region are formed before bonding semiconductor structures, then proper electrical isolation and device functionality are achieved, but process complexity and manufacturing cost increase
Solution Approach 1:
The patent applies preliminary action by forming the separation insulating pattern on the second substrate before bonding the first and second substrates. This pre-formed insulating structure is then integrated into the final device through the bonding process, eliminating the need for subsequent SSL-cut and GSL-cut region formation while maintaining proper electrical isolation. The separation insulating pattern serves as a pre-prepared structural element that simplifies the overall manufacturing process.
2Reliability
If SSL-cut region and GSL-cut region are formed before bonding semiconductor structures, then proper electrical isolation and device functionality are achieved, but manufacturing cost increases
Solution Approach 1:
The separation insulating pattern is formed in advance on the second substrate, allowing for cost-effective batch processing. This preliminary formation eliminates the need for expensive and complex SSL-cut and GSL-cut region formation steps that would otherwise be required after bonding, thereby reducing overall manufacturing cost while maintaining electrical isolation reliability.
3Device complexity
If separation insulating patterns are formed after bonding semiconductor structures, then process complexity is reduced, but integration precision must be maintained
Solution Approach 1:
By forming the separation insulating pattern on the second substrate before bonding, the patent ensures that the insulating structure is precisely positioned in advance. This preliminary positioning maintains high integration precision because the pattern is formed on a single substrate where alignment is easier to control, rather than attempting to form it after bonding two substrates together.
Data Source
AI summary
A semiconductor device includes a first semiconductor structure including circuit elements on a first substrate, a lower interconnection structure on the circuit elements, and a lower bonding structure on the lower interconnection structure; and a second semiconductor structure including a second substrate on the first semiconductor structure, separation insulating patterns separating the second substrate, and disposed to be spaced apart from each other, gate electrodes stacked to be spaced apart from each other, separation regions passing through the gate electrodes, and disposed to be spaced apart from each other, channel structures passing through the gate electrodes, an upper interconnection structure below the gate electrodes, and an upper bonding structure bonded to the lower bonding structure, wherein the separation insulating patterns include first separation insulating patterns on the separation regions, and second separation insulating patterns between the channel structures and passing through the second substrate.