Bypass Buffer System for NoC Congestion Mitigation
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Solution Overview
Problem
Existing network-on-chip (NoC) designs face challenges with routing-level deadlocks and head-of-line (HoL) blocking, which can lead to performance issues and increased hardware complexity.
Innovation Solution
The implementation of a bypass buffer system that allows packets to bypass input memory and directly access output buffers, reducing HoL blocking and eliminating the need for multiple virtual channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple virtual channels are used to prevent routing-level deadlocks, then reliability is improved, but device complexity increases due to increased number of wirings and cell count
Solution Approach 1:
The patent extracts the packet storage function from the input port and places it in a shared memory pool. This separates the buffering function from the routing logic, allowing packets to be stored centrally and accessed by multiple output ports without requiring complex virtual channel management at each input port.
Solution Approach 2:
The shared memory pool serves multiple output ports simultaneously, making a single resource universal. Instead of dedicating separate buffers and virtual channels to each input-output pair, the shared memory pool can be accessed by any output port that needs to send packets, reducing overall hardware complexity while maintaining reliability.
2Device complexity
If packets are stored in input memory waiting for output port availability, then head-of-line blocking occurs, but device complexity is reduced
Solution Approach 1:
The patent segments the traditional input port structure by separating the storage function (shared memory pool) from the output function (output ports). Packets are stored in the shared memory pool independently of any specific output port, allowing different packets to be served by different output ports without blocking each other, thus eliminating head-of-line blocking while maintaining simple hardware design.
3Productivity
If bypass buffer is implemented to allow direct access from input ports to output buffers, then throughput is improved by eliminating HoL blocking, but device complexity increases
Solution Approach 1:
The patent merges the bypass buffer functionality into the shared memory pool structure. Instead of implementing separate bypass buffers for each input port, the shared memory pool itself serves as the bypass mechanism, allowing packets to be directly accessed by output ports without traditional buffering stages. This combines multiple functions into a single unified structure, improving throughput without proportionally increasing complexity.
Data Source
AI summary
Examples described herein relate to switch circuitry that is to: based on receipt of a packet at the first input port and based on allocation of a first memory region in the memory to the first input port: based on capability of a first buffer for the first output port to store the packet, store the packet into the first buffer and egress the packet from the first buffer to the first output port and based on incapability of the first buffer to store the packet, store the packet into the first memory region and associate the packet with the first buffer prior to egress from the first output port.