Bypass Capacitor Arrangement Verification for PCB Layout
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Solution Overview
Problem
Existing techniques for arranging bypass capacitors on printed circuit boards fail to verify the arrangement with high accuracy, particularly due to the neglect of in-package wiring within integrated circuits, leading to potential noise issues and malfunction.
Innovation Solution
An information processing apparatus that specifies power source and ground pads of a die, identifies bypass capacitors, and evaluates their arrangement based on design information, considering both the die and package wiring to determine the appropriateness of the capacitor placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If in-package wiring is not taken into account, then the verification process is simpler and faster, but the accuracy of bypass capacitor arrangement verification deteriorates
Solution Approach 1:
The patent applies nesting by integrating in-package wiring information within the IC package model, which is then nested within the overall PCB design information. This hierarchical nesting allows the verification system to access detailed in-package wiring paths without requiring separate complex verification processes, thereby improving accuracy while managing complexity through structured data organization.
Solution Approach 2:
The patent introduces an intermediary data structure that bridges PCB-level design information and in-package wiring information. This intermediary layer enables the verification unit to access and process detailed in-package wiring paths without directly complicating the PCB verification process, allowing accurate verification while maintaining a clear separation between different levels of design complexity.
2Reliability
If only PCB wiring is considered, then the verification process is easier to implement, but the noise suppression effectiveness deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-defining in-package wiring information and power source pad locations within the IC package model before the bypass capacitor arrangement verification is performed. This preliminary preparation of detailed wiring data enables accurate noise suppression verification without requiring complex real-time analysis during the verification process, thus improving reliability while maintaining ease of implementation.
3Measurement precision
If detailed in-package wiring information is included, then the evaluation accuracy improves, but the data processing requirements increase
Solution Approach 1:
The patent applies local quality by focusing the detailed in-package wiring information specifically on the power source pad connections and relevant signal paths within the IC package. Rather than including all possible wiring information, the system selectively processes only the locally relevant wiring data that directly impacts bypass capacitor arrangement evaluation, thereby improving accuracy while minimizing data processing requirements.
Data Source
AI summary
In a layout design of a printed circuit board, more accurate bypass capacitor arrangement that has taken into consideration a wiring within a package of an IC is implemented. An information processing apparatus according to the present invention includes: a die pad specifying unit configured to specify a power source pad of a die and a ground pad of the die from design information on a printed circuit board; a bypass capacitor specifying unit configured to specify a bypass capacitor that is arranged on the printed circuit board from the design information; and a unit configured to derive an evaluation value for evaluating the arrangement of the specified bypass capacitor based on the design information, information on the specified power source pad of the die and ground pad of the die, and information on the specified bypass capacitor.