Bypass Circuit for Remote Pin Electronics Signal Integrity
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Solution Overview
Problem
Devices with small form factors or high input/output (I/O) densities pose challenges in placing pin electronics close to the device under test, forcing designers to choose between a full spectrum of test functions at a distance or a reduced set at a closer location, leading to signal degradation issues.
Innovation Solution
A remote pin electronics block coupled with a bypass circuit, enabling the control of signal paths between a tester I/O node and a device under test I/O node, allowing for the implementation of test functions closer to the DUT while providing a signal bypass path to minimize signal degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pin electronics are placed closer to the device under test, then signal degradation is reduced, but the device complexity increases due to limited space and high I/O density
Solution Approach 1:
The pin electronics are divided into two separate blocks: a first pin electronics block placed close to the DUT for signal generation and a second pin electronics block placed remotely for signal processing. This segmentation allows each block to be optimized for its specific function while resolving the space constraint at the DUT location.
Solution Approach 2:
A test circuit is introduced as an intermediary component that couples the first and second pin electronics blocks. The test circuit includes a first circuit portion near the DUT and a second circuit portion remotely, with signal paths connecting them, thereby enabling signal transmission between separated electronics blocks.
2Device complexity
If a full spectrum of test functions is implemented at a location farther from the DUT, then device complexity is reduced, but signal degradation increases over the longer signal path
Solution Approach 1:
The pin electronics are divided into two separate blocks: a first pin electronics block placed close to the DUT for signal generation and a second pin electronics block placed remotely for signal processing. This segmentation allows each block to be optimized for its specific function while resolving the space constraint at the DUT location.
Solution Approach 2:
A test circuit is introduced as an intermediary component that couples the first and second pin electronics blocks. The test circuit includes a first circuit portion near the DUT and a second circuit portion remotely, with signal paths connecting them, thereby enabling signal transmission between separated electronics blocks.
3Reliability
If a reduced set of test functions is implemented closer to the DUT, then signal degradation is minimized, but the functionality is limited
Solution Approach 1:
The pin electronics are divided into two separate blocks: a first pin electronics block placed close to the DUT for signal generation and a second pin electronics block placed remotely for signal processing. This segmentation allows each block to be optimized for its specific function while resolving the space constraint at the DUT location.
Solution Approach 2:
The second pin electronics block, located remotely, is designed to provide a full spectrum of test functions including signal generation, processing, and evaluation. This multi-functional design ensures that all required test capabilities are available while maintaining signal quality through the distributed architecture.
Data Source
AI summary
In one embodiment, apparatus for testing at least one device under test (DUT) includes a tester input/output (I/O) node, a DUT I/O node, a remote pin electronics block, a bypass circuit, and a control system. The remote pin electronics block provides a test function and is coupled between the tester I/O node and the DUT I/O node. The bypass circuit is coupled between the tester I/O node and the DUT I/O node and provides a signal bypass path between the tester I/O node and the DUT I/O node. The signal bypass path bypasses the test function provided by the remote pin electronics block. The control system is configured to enable and disable the bypass circuit. Methods for using this and other related apparatus to test one or more DUTs are also disclosed.


