Bypass Control Unit for Operation Processing Device Power Reduction
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Solution Overview
Problem
Operation processing devices with CMOS circuits experience increased power consumption due to through current when address signals change, particularly when transferring data from a register file to an operand register.
Innovation Solution
The device incorporates a bypass control unit that generates a bypass selection signal to selectively transfer data directly from the operation unit to the operand register without passing through the register file, and stops the timing adjustment unit's operation when a bypass transfer is executed, thereby reducing the transition of read address signals and minimizing through current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If data is transferred from register file to operand register using traditional pipeline process, then data integrity is ensured, but power consumption increases due to through current in CMOS circuits
Solution Approach 1:
The patent extracts the harmful through current flow from the data transfer path by introducing a bypass mechanism. When a bypass transfer is executed, data is transferred directly from the register file to the operand register without passing through the selection unit, thereby eliminating the address signal transitions that cause through current in CMOS circuits while maintaining data transfer reliability.
Solution Approach 2:
The patent introduces a bypass control unit as an intermediary that monitors write address signals and generates bypass transfer control signals. This intermediary component enables the system to selectively activate bypass paths, reducing power consumption during data transfers while ensuring data integrity through controlled bypass operations.
2Loss of energy
If bypass transfer is executed to reduce power consumption, then through current is minimized, but processing delay may increase without proper timing control
Solution Approach 1:
The bypass control unit performs preliminary actions by monitoring write address signals in advance and generating bypass transfer control signals before data transfer operations commence. This advance preparation ensures that bypass transfers are executed at optimal timing, minimizing both power consumption and processing delay by pre-coordinating the bypass path activation with the data flow requirements.
Solution Approach 2:
The patent implements dynamic control of the data transfer path by selectively switching between traditional pipeline transfer and bypass transfer modes. The bypass control unit dynamically generates control signals based on write address signal patterns, enabling the system to adaptively optimize the balance between power consumption and processing speed for each data transfer operation.
3Adaptability or versatility
If address signals are frequently transmitted for data selection, then data access flexibility is improved, but power consumption increases due to through current
Solution Approach 1:
The patent removes the source of through current by extracting address signal transmissions from the data access path during bypass operations. The bypass control unit detects when bypass transfers are applicable and eliminates unnecessary address signal transmissions to the selection unit, thereby maintaining data access flexibility through selective bypass activation while significantly reducing power consumption.
Solution Approach 2:
The patent changes the operational parameter of address signal transmission by conditionally disabling it during bypass transfers. The bypass control unit modifies the transmission state of address signals based on write address signal patterns, allowing the system to switch between high-flexibility mode (traditional access with address signals) and low-power mode (bypass access without address signals), thus optimizing the balance between adaptability and power consumption.
Data Source
AI summary
An operation processing device includes a first register unit including first registers configured to hold data to be used for an operation in an operation unit; a first selection unit that selects data held by a first register indicated by a read address signal; a second selection unit that selects, based on a bypass selection signal, data from a data group including the data selected by the first selection unit and data indicative of a result of the operation; a second register unit that outputs the data selected by the second selection unit to the operation unit; a timing adjustment unit that outputs the read address signal to the first selection unit; and a bypass control unit that stops an operation of the timing adjustment unit when generating the bypass selection signal indicative of a selection of data other than the data selected by the first selection unit.