Bypassing Encoded Latches for ECC Test Pattern Generation
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Solution Overview
Problem
Testing integrated circuits with error checking and correcting (ECC) protected logic is challenging due to the difficulty in generating correct ECC check bits during random pattern testing, as ECC codes increase code space and often result in incorrect check bits, making thorough testing inefficient.
Innovation Solution
A method is implemented to bypass encoded latches during a test-pattern scan, using on-chip circuitry to generate and insert correct ECC check bits, allowing for thorough testing of ECC protected logic by initializing the scan with correct ECC check bits generated by the chip's ECC generation logic, rather than random patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If random pattern testing is used to test ECC protected logic, then the testing process is simple and fast, but the test effectiveness is poor because most patterns produce incorrect check bits
Solution Approach 1:
The patent applies preliminary action by pre-generating valid ECC check bit patterns using the chip's own ECC generation logic before applying test patterns. This ensures that when test patterns are applied to ECC protected logic, the corresponding check bits are already in the correct state, making the testing both efficient and effective. The system prepares the necessary conditions (correct check bit patterns) in advance rather than relying on random patterns to accidentally produce valid combinations.
2Reliability
If thorough testing of ECC logic is performed using random patterns, then test coverage improves, but the time and resources required increase significantly
Solution Approach 1:
The patent implements self-service by utilizing the chip's built-in ECC generation logic to create test patterns with correct check bits. Instead of requiring external test equipment to generate and verify complex ECC patterns, the chip itself generates the necessary check bit patterns, reducing external testing resources and time while maintaining thorough test coverage.
3Reliability
If ECC check bits are generated using on-chip circuitry during testing, then correct patterns are produced, but additional testing steps are required
Solution Approach 1:
The patent applies universality by designing the scan path and ECC generation logic to serve dual purposes: normal operational functionality and test pattern generation. The same on-chip ECC generation logic that operates during normal chip function is also utilized during testing to generate valid check bit patterns, eliminating the need for separate test-specific ECC generation circuitry and reducing overall testing procedure complexity.
Data Source
AI summary
Aspects include techniques for bypassing an encoded latch on a chip during a test-pattern scan and using on-chip circuitry to generate a desired encoded pattern, which is inserted into a scan-bypassed latch, to test the on-chip circuitry for defects. A computer-implemented method may include applying a global control bit to the chip; initializing a scan of the chip while bypassing the encoded latch; and applying an extra scan clock to initiate the encoded latch after completing the scan, wherein the encoded latch is updated with check bits generated by the on-chip circuitry.