Bypass Power Supply Circuit With Boot Capacitor Discharge
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Solution Overview
Problem
Existing power supply circuits face challenges in achieving low quiescent current during bypass mode, which affects accuracy in current leakage measurements, and current reduction techniques often introduce circuit complexity and performance issues.
Innovation Solution
The power supply circuit discharges the boot capacitor before entering bypass mode or determines it is already discharged, using a pullup circuit to turn on the high-side power transistor without gate driver assistance, thereby reducing quiescent current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If the charge pump circuit is enabled to boost the reference voltage, then the reference voltage level is sufficient for the phase detector, but the quiescent current consumption increases
Solution Approach 1:
The charge pump circuit is designed to dynamically switch between enabled and disabled states based on the operational mode detected by the mode detector. In bypass mode, the charge pump is disabled to minimize current consumption. In normal mode, the charge pump is enabled to provide the necessary voltage boost, thus adapting the system behavior to operational requirements.
Solution Approach 2:
The system changes the operational parameter (charge pump enable/disable state) based on the detected mode. The mode detector identifies whether the PLL is in bypass or normal mode, and accordingly, the charge pump's operational state is changed to optimize between voltage level requirements and current consumption constraints.
2Use of energy by stationary object
If the charge pump circuit is disabled to reduce current consumption, then quiescent current is minimized, but the reference voltage level becomes insufficient for proper phase detector operation
Solution Approach 1:
The charge pump circuit transitions dynamically between disabled and enabled states based on mode detection. In bypass mode, it remains disabled to minimize current consumption. When normal mode is detected, it enables the charge pump to provide the necessary voltage boost, thus dynamically adapting to operational requirements.
Solution Approach 2:
The system changes the charge pump's operational state parameter based on the detected mode. The mode detector identifies the operational mode, and the charge pump's enable/disable parameter is changed accordingly to balance between current consumption and voltage level requirements.
3Use of energy by stationary object
If the PLL operates in bypass mode for low-power applications, then power consumption is reduced, but the voltage level from the reference voltage generator is insufficient
Solution Approach 1:
The mode detector acts as an intermediary that monitors the operational state and triggers the appropriate response. When bypass mode is detected, it activates the voltage boosting circuit to compensate for the insufficient voltage level, thus mediating between the low-power requirement and the voltage level requirement.
Solution Approach 2:
The system anticipates the voltage insufficiency issue in bypass mode by implementing a preliminary voltage boosting mechanism. When bypass mode is detected, the voltage boosting circuit is activated in advance to prevent the voltage level from being insufficient, thus counteracting the potential harmful effect before it occurs.
Data Source
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Figure 3A
AI summary
Power supply circuit having low quiescent current for a bypass mode. One example power supply circuit generally includes a transistor; a switching node coupled to a source of the transistor; a power supply rail; a capacitor having a first terminal coupled to the power supply rail and having a second terminal coupled to the switching node; a gate driver having an output coupled to a gate of the transistor, having a first power input coupled to the power supply rail, and having a second power input coupled to the switching node; logic having a first input coupled to the first terminal of the capacitor, having a second input coupled to the second terminal of the capacitor, and having a first output; and a pullup circuit having a control input coupled to a second output of the logic and having an output coupled to the gate of the transistor.