Bypass Routing for Deadlock-Free Modular Multi-Chiplet Systems
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Solution Overview
Problem
Existing deadlock-free designs for 2.5D multi-chiplet systems face limitations in network performance, high overhead, and restrictions on border router selection, compromising path diversity and scalability, while traditional 2D packaging methods do not support modular design requirements in multi-chiplet architectures.
Innovation Solution
A method involving time slice round-robin scheduling to poll border routers, triggering a bypass mechanism for choked packets, and using a look-ahead signal to reserve output ports, ensuring that data packets forwarded by an interposer reach their destination without additional buffers or synchronization protocols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional 2D packaging deadlock-free methods are used in each chiplet and interposer, then intra-chiplet deadlock is avoided, but inter-chiplet deadlock occurs due to multiple chiplets being integrated together
Solution Approach 1:
The patent segments the deadlock avoidance mechanism into two independent parts: intra-chiplet routing (handled by traditional methods) and inter-chiplet routing (handled by the new bypass mechanism). This segmentation allows each chiplet to be designed independently while the bypass mechanism handles the inter-chiplet connectivity, enabling modular design without sacrificing deadlock avoidance.
Solution Approach 2:
The patent introduces a bypass mechanism as an intermediary component between chiplets. This bypass mechanism acts as a mediator that handles inter-chiplet data packets separately from intra-chiplet traffic, allowing the two types of traffic to be managed independently and preventing inter-chiplet deadlock without affecting the modular design of individual chiplets.
2Reliability
If existing deadlock-free designs for 2.5D multi-chiplet systems are used, then deadlock is avoided, but network performance is limited and overhead increases
Solution Approach 1:
The patent applies partial action by implementing the bypass mechanism only for inter-chiplet data packets that require it, rather than applying a comprehensive deadlock avoidance strategy to all packets. This selective approach reduces overhead while maintaining deadlock freedom, as the bypass is activated only when necessary to handle inter-chiplet traffic.
Solution Approach 2:
The patent implements preliminary action by pre-establishing the bypass mechanism in the routing architecture before deadlock conditions arise. The bypass is prepared in advance as part of the routing structure, allowing inter-chiplet packets to be routed efficiently without needing to react to deadlock conditions dynamically, thus improving performance while maintaining reliability.
3Reliability
If existing deadlock-free designs restrict border router selection, then deadlock is avoided, but path diversity is compromised
Solution Approach 1:
The patent applies local quality by implementing different routing strategies for different types of packets: intra-chiplet packets use traditional routing with border router selection, while inter-chiplet packets use the bypass mechanism. This localized differentiation allows each routing path to be optimized for its specific requirements, maintaining deadlock avoidance where needed while preserving routing flexibility where beneficial.
Solution Approach 2:
The patent introduces dynamics to the routing system by making the routing path selection adaptive based on packet type and destination. The system can dynamically switch between traditional routing and bypass routing depending on the specific traffic conditions and requirements, providing flexibility while maintaining deadlock avoidance capabilities.
4Reliability
If additional buffers and synchronization protocols are added to solve deadlock, then deadlock is avoided, but device complexity increases
Solution Approach 1:
The patent extracts the deadlock avoidance function from the traditional routing mechanism and places it in a separate bypass mechanism. This extraction allows the bypass to handle inter-chiplet deadlock independently without requiring additional buffers or synchronization protocols in the traditional routing paths, thus reducing overall device complexity while maintaining deadlock freedom.
Solution Approach 2:
The bypass mechanism is designed to be self-sufficient, handling inter-chiplet deadlock avoidance without requiring external assistance from additional buffers or synchronization protocols. The mechanism uses the existing routing infrastructure and packet forwarding capabilities to achieve deadlock freedom, eliminating the need for complex additional components.
Data Source
AI summary
A method and system for solving bypass-based modular multi-chiplet deadlock include polling each border router by means of time slice round-robin scheduling inside each chiplet; when processing upon arrival of the time slice of the border router, the border router is polled based on the internal time slice of the chiplet in a switchover manner to trigger the bypass mechanism of choke packets, and an output port is reserved between the border router and the destination router by using a look-ahead signal to build a bypass, and reserving a network interface and a rollback mechanism when the bypass packet pops up. The present disclosure aims at achieving deadlock-free in realizing bypass-based modular multi-chiplet design requirements in a multi-chiplet architecture under 2.5D packaging.