Bypass Switch for Active Ethernet Cable Debugging

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Solution Overview

Problem

As data rates increase beyond 50 Gbps, existing Ethernet standards face challenges in maintaining robust performance over extended distances due to channel attenuation and dispersion, requiring costly active optical cables and complicating debugging and verification processes through additional hardware layers.

Innovation Solution

The development of an active Ethernet cable with integrated data recovery and re-modulation (DRR) devices and controllers, featuring a bypass switch to merge command and configuration buses, enabling direct access for debugging and testing, and utilizing automated test equipment for optimizing equalization filter coefficients.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If active optical cable (AOC) designs are used for distance spans greater than 2 meters, then data transport capability is improved, but cost increases prohibitively

Engineering Contradiction:
Improvedistance spanVSAvoidcost
Core Design Contradiction:
Length of moving objectVSReliability

Solution Approach 1:

The patent employs affordable active Ethernet cable (AEC) with integrated DRR chips and supporting circuitry in cable connectors instead of expensive active optical cables. This substitution uses cost-effective copper-based transmission with embedded data recovery and remodulation functionality, achieving comparable performance at lower cost for distance spans up to at least seven meters

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The cable system is segmented into distinct functional modules: DRR devices in cable connectors, supporting circuitry, and host interface ports. This segmentation allows independent optimization of each component and enables flexible configuration for different distance requirements without requiring complete system redesign

Inventive Principle:
Principle #1Segmentation

2Length of moving object

If DRR chips and supporting circuitry are added to cable connectors, then data transport over extended distances is enabled, but device complexity increases

Engineering Contradiction:
Improvedistance spanVSAvoidhardware layers
Core Design Contradiction:
Length of moving objectVSDevice complexity

Solution Approach 1:

The patent merges multiple functions into integrated DRR chips and supporting circuitry located in cable connectors. These integrated components combine data recovery, remodulation, and control functions, reducing the need for separate discrete components and simplifying the overall system architecture despite enabling extended distance transmission

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The DRR devices in cable connectors perform self-configuration and self-testing through built-in controller devices that can directly access configuration buses. This self-service capability reduces the need for external configuration equipment and simplifies deployment complexity

Inventive Principle:
Principle #25Self-service

3Reliability

If integrated modules for built-in self-test (BIST) and debugging support are added, then product verification capability is improved, but access difficulty increases due to additional hardware layers

Engineering Contradiction:
Improveproduct verificationVSAvoidaccess difficulty
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The patent extracts debugging and configuration access directly to the host interface port through a bypass switch that can merge the command bus with the configuration bus. This extraction eliminates the need to navigate through multiple intermediate hardware layers and controller interfaces, allowing direct access to DRR device configuration and testing functions

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The bypass switch acts as an intermediary that can selectively connect the host interface port directly to the configuration bus, bypassing the normal controller device interface hierarchy. This intermediary mechanism provides direct access paths for debugging and verification without requiring traversal of multiple software and hardware layers

Inventive Principle:
Principle #24Intermediary (Mediator)

4Loss of time

If direct access to configuration bus is enabled via bypass switch, then debugging and verification time is reduced, but hardware control complexity increases

Engineering Contradiction:
Improvedebugging and verification timeVSAvoidswitch control
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The bypass switch is designed with dynamic control capability, allowing it to be selectively activated or deactivated based on operational mode. During normal operation, the switch remains inactive maintaining standard control paths. During debugging or verification modes, the switch dynamically reconfigures to provide direct host access to the configuration bus, reducing debugging time without permanently increasing control complexity

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11137550B2Bypass switch for managing active ethernet cable
Publication Date: 2021.10.05 CREDO TECHNOLOGY GROUP LTD
  • US11137550B2 patent drawing
  • US11137550B2 patent drawing
  • US11137550B2 patent drawing

AI summary

A cable, a manufacturing method, and a usage method, each facilitate product development, testing, and debugging. An illustrative embodiment of a cable manufacturing method includes: connecting a first end connector plug to a first data recovery and re-modulation (DRR) device and to a first controller device; and providing a bypass switch that operates under control of the first controller device to merge the command bus with the configuration bus, thereby enabling direct access to the configuration bus by the first host interface port. The first end connector plug has: a set of dedicated pins for conveying mufti-lane data streams between the first DRR device and a first host interface port; and additional pins for a two-wire command bus conveying communications between the first host interface port and a first controller device, the first controller device operable to configure the first DRR device via a two-wire configuration bus.