Bypassing Volatile Memory in Persistent Write Transactions
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Solution Overview
Problem
In multi-level memory systems, write transactions often require data to be cached in volatile memory before being written to non-volatile memory, leading to increased power consumption, latency, and reduced availability of volatile memory for caching, as they involve additional device input/output operations and cache evictions.
Innovation Solution
A memory controller system that receives a signal to bypass volatile memory by directing data directly to a persistent memory device, utilizing a write buffer in the persistent-memory controller for temporary storage if available, thereby reducing the need for volatile memory access and optimizing power and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If data is cached in volatile memory before being written to non-volatile memory, then data retention is improved, but power consumption increases and latency increases
Solution Approach 1:
The patent extracts the volatile memory caching step from the traditional write path. By using write-in-place persistent memory, data is written directly to non-volatile storage without being cached in volatile memory first, eliminating the energy-consuming volatile memory access operations while maintaining data persistence.
Solution Approach 2:
The patent introduces a write buffer as an intermediary component between the memory controller and persistent memory. This buffer temporarily holds write data, allowing the system to batch writes and reduce the frequency of volatile memory accesses, thereby reducing power consumption while ensuring data is eventually persisted.
2Stability of the object's composition
If data is cached in volatile memory before being written to non-volatile memory, then data retention is improved, but latency increases
Solution Approach 1:
The patent removes the volatile memory caching intermediate step from the write path. Data is written directly to write-in-place persistent memory, eliminating the time required for volatile memory access, cache management, and data transfer between memory levels, thus reducing overall latency.
Solution Approach 2:
The system performs preliminary actions by maintaining a write buffer that pre-processes and batches write operations. This allows the system to prepare data for persistence in advance, reducing the critical path latency for individual write operations while ensuring data is eventually written to persistent storage.
3Stability of the object's composition
If data is cached in volatile memory before being written to non-volatile memory, then data retention is improved, but volatile memory availability for caching decreases
Solution Approach 1:
The patent extracts data from the volatile memory caching hierarchy by writing directly to persistent memory. This eliminates the need to occupy volatile memory capacity with data intended for long-term storage, freeing up volatile memory resources for their primary caching function and improving overall memory system adaptability.
Data Source
AI summary
Embodiments of the present disclosure relate to an apparatus, comprising a first memory controller, to receive a signal from a component coupled with the first memory controller, where the signal indicates that data is to bypass a volatile memory device coupled with the first memory controller and be written to a byte-addressable write-in-place persistent memory device coupled with the first memory controller; determine, in response to the received signal, whether a write buffer in a second memory controller, coupled with the first memory controller, is empty; direct, if the write buffer is empty, the data to the write buffer for temporary storage prior to storage in the persistent memory device, to bypass the volatile memory device; and direct, if the write buffer is not empty, the data to the volatile memory device.