Bypassable Flip-Flop Routing to Expand FPGA Placement Resources

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Solution Overview

Problem

Current programmable logic integrated circuit architectures have unplaced input flip-flops that are not available for placement in circuit designs, limiting the available flip-flop count for programmable logic fabric architectures.

Innovation Solution

A configurable bypassable flip-flop circuit is introduced, connected to a loopback branch and multiplexer, allowing it to be placed in the circuit design by routing information through programmable internal routing and bypassing the programmable logic circuit, thereby increasing the available flip-flop count.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If unplaced input flip-flops are not made available for placement, then the circuit block structure is maintained, but the available flip-flop count for programmable logic fabric is limited

Engineering Contradiction:
Improveavailable flip-flop countVSAvoidcircuit block structure
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent extracts the flip-flop functionality from the constrained circuit block structure by providing a bypass path that allows flip-flops to be placed independently in the programmable logic fabric without requiring their associated circuit blocks to be placed. This separation enables the flip-flop count to be increased without being limited by circuit block placement requirements.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a bypass multiplexer as an intermediary component that mediates between the flip-flop output and the programmable logic fabric. This intermediary allows signals to pass through the flip-flop without requiring the associated circuit block to be placed, effectively decoupling the flip-flop availability from circuit block placement constraints.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If additional flip-flop circuits are inserted, then pipelining capabilities are enhanced, but the circuit design complexity increases

Engineering Contradiction:
Improvepipelining capabilitiesVSAvoidcircuit design
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The bypass multiplexer serves multiple functions: it enables flip-flop placement in unplaced circuit blocks, provides pipelining capabilities, and maintains compatibility with existing circuit block structures. This multi-functionality allows additional flip-flops to be inserted to enhance pipelining without proportionally increasing overall circuit design complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Quantity of substance

If flip-flops are made available in unplaced circuit blocks, then the effective flip-flop count increases, but the routing complexity increases

Engineering Contradiction:
Improveeffective flip-flop countVSAvoidrouting structure
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The bypass multiplexer acts as an intermediary that simplifies routing by providing a direct connection path from flip-flop outputs to the programmable logic fabric, avoiding the need for complex routing through unplaced circuit blocks. This intermediary structure enables increased flip-flop availability while managing routing complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10387594B1Increasing available flip-flop count for placement of a circuit design in programmable logic and circuitry therefor
Publication Date: 2019.08.20 XILINX INC
  • US10387594B1 patent drawing
  • US10387594B1 patent drawing
  • US10387594B1 patent drawing

AI summary

An integrated circuit having programmable logic fabric, as well as system and method for computer aided design using such integrated circuit, are disclosed. This integrated circuit includes: a configurable bypassable flip-flop circuit configured to transfer information from programmable internal routing to an input bus of a programmable logic circuit; a loopback branch connected to the input bus to bypass the programmable logic circuit; and a multiplexer having a first input port connected to the loopback branch, a second input port connected to an output bus of the programmable logic circuit, and an output port connected to routing switches of the programmable internal routing. The multiplexer is configured to electrically couple either the first input port or the second input port to the output port.