Bypassable Scan Chains for Low Test Mode Power
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Solution Overview
Problem
Integrated circuit testing using scan chains consumes excessive power, leading to thermal issues and prolonged test times, as many flip-flops toggle during scanning, which is not present during operational modes, and reducing clock frequency increases test time without reducing peak power.
Innovation Solution
The solution involves selectively bypassing serial scan chains and loading them with constant or low-toggle data, such as all 0s or all 1s, to minimize power consumption, and dynamically changing the number and identity of bypassed chains based on semiconductor process variations, ensuring optimal testing across different integrated circuit designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scan chains are used to load test data serially into flip-flops, then test coverage is achieved, but power consumption increases due to excessive flip-flop toggling
Solution Approach 1:
The invention divides scan chains into groups and selectively activates only certain groups during testing. By segmenting the scan chains and using control logic to enable/disable specific groups, the patent reduces the number of active flip-flops during test mode, thereby lowering power consumption while maintaining adequate test coverage through strategic selection of which scan chain groups to activate.
Solution Approach 2:
The patent applies partial action by loading scan chains with constant values (all 0s or all 1s) instead of alternating patterns. This causes flip-flops to toggle minimally (only during the transition from constant to test pattern), significantly reducing dynamic power consumption while still enabling comprehensive fault detection through the test patterns that follow.
2Use of energy by moving object
If scan chains are bypassed to reduce power consumption, then power and thermal issues are mitigated, but test time increases due to slower scanning
Solution Approach 1:
The patent employs periodic action by alternating between different scan chain group configurations across multiple test cycles. Different groups of scan chains are activated in different cycles, allowing the system to maintain lower average power consumption while ensuring comprehensive coverage over time. This periodic rotation of active scan chain groups balances power reduction with test completeness.
Solution Approach 2:
The invention introduces dynamic control through logic that selectively enables or disables scan chain groups based on test requirements. This dynamic configuration allows the system to adaptively manage power consumption during different phases of testing, activating only the necessary scan chain groups for each specific test objective, thereby optimizing both power efficiency and test time.
3Power
If scan chains are bypassed with constant data, then peak power is reduced, but the ability to test all circuit states is compromised
Solution Approach 1:
The patent segments scan chains into multiple groups that can be independently controlled. By selectively activating different groups for different test objectives, the system maintains peak power reduction through constant data loading in inactive groups while ensuring comprehensive test coverage through strategic activation of appropriate groups for specific fault detection tasks.
Solution Approach 2:
The invention introduces control logic as an intermediary between the test pattern generator and scan chains. This intermediary selectively routes constant data or test patterns to different scan chain groups based on test requirements, thereby mediating between the conflicting goals of peak power reduction and comprehensive test coverage by directing constant data only to groups that don't require active testing at that moment.
Data Source
AI summary
This invention permits selectively bypasses serial scan chains. Constant or low toggle data is directed to the bypassed serial scan chain, thus reducing power consumption. The number and identity of serial scan chains bypassed during a particular test can be changed dynamically dependent upon the semiconductor process variations of a particular integrated circuit. This enables an optimal test to be preformed for integrated circuits having differing semiconductor process variations.