Bypassable Clocked Storage Circuitry for Flexible DVFS Timing
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Solution Overview
Problem
Conventional dynamic voltage-frequency scaling (DVFS) schemes in integrated circuits are limited by fixed voltage-frequency relationships determined at design time, which restrict the ability to adjust operating frequencies and voltages post-fabrication, hindering efficient power management and performance optimization across varying workload conditions.
Innovation Solution
The integration of bypassable clocked storage elements and combinational logic delay elements with dynamic voltage-frequency scaling control circuitry allows for adjustable power supply voltages and clock frequencies, enabling operation at different voltage-frequency states without reconfiguration, thereby optimizing power consumption and performance through selective enabling of registers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional DVFS schemes are used with fixed voltage-frequency relationships, then the circuit structure is simple and design-time determination is straightforward, but the ability to adjust operating frequencies and voltages post-fabrication is restricted
Solution Approach 1:
The patent applies dynamics by making the previously fixed voltage-frequency relationship adjustable. The control circuit dynamically selects different operating points (voltage and frequency combinations) based on workload conditions, transforming a static design-time configuration into a runtime-adaptable system. This is achieved through bypassable registers that can be selectively enabled or disabled to adjust the effective logic path delay, allowing frequency adjustment independent of the fixed combinational logic delay.
Solution Approach 2:
The patent changes the operating parameters (voltage and frequency) dynamically based on workload conditions. By introducing bypassable registers, the system can alter the effective propagation delay parameter of the logic path, enabling frequency adjustment without changing the physical circuit structure. The control circuit modifies these parameters in real-time to optimize power consumption while maintaining performance requirements.
2Productivity
If the maximum operating frequency is limited by combinational logic delay, then the circuit design is straightforward with fixed timing, but the frequency cannot be adjusted after fabrication to optimize for different workload conditions
Solution Approach 1:
The patent segments the logic path by inserting bypassable registers at strategic points within the combinational logic. This segmentation divides the fixed-delay logic path into multiple smaller segments separated by controllable storage elements. By selectively bypassing certain segments, the system can adjust the effective delay and thus the operating frequency, transforming a monolithic fixed-frequency design into a flexible multi-frequency system.
Solution Approach 2:
The bypassable registers act as intermediaries between the input and output of the combinational logic path. These intermediary elements can be selectively enabled or disabled to adjust the total propagation delay. When enabled, they add controlled delay; when bypassed, they allow faster signal propagation. This intermediary mechanism enables frequency adjustment without modifying the core combinational logic structure.
3Loss of energy
If more bypassable registers are enabled to allow lower voltage operation, then power consumption is reduced, but the latency increases due to additional clock cycles
Solution Approach 1:
The patent applies partial action by selectively enabling only the necessary number of bypassable registers required to achieve the desired voltage reduction, rather than enabling all possible registers. The control circuit calculates the minimum number of bypass registers needed to create sufficient delay for the reduced voltage operation, thereby minimizing the latency penalty while still achieving power savings. This partial activation optimizes the trade-off between power consumption and latency.
Data Source
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AI summary
Integrated circuits (10) with sequential logic circuitry are provided. Sequential logic circuitry may include a chain of bypassable clocked storage elements (R0 to R4) coupled between a speed critical input terminal (102) and a speed critical output terminal (104). Combinational logic circuits (106) may be interposed between each adjacent pair of bypassable clocked storage elements in the chain. Dynamic voltage-frequency scaling (DVFS) control circuitry may provide an adjustable power supply voltage (Vcc) to the combinational logic circuits (106) and may provide an adjustable clock signal (CLK) to control the clocked storage elements (R0, R4). The DVFS control circuitry may be used to selectively enable at least some of the bypassable clocked storage elements (R0,R4) while disabling other bypassable clocked storage elements (R1, r2, R3) so that the power supply voltage (Vcc) can be reduced while maintaining the same operating frequency (CLK). The power supply voltage and the frequency of the clock signal can be adjusted to provide the desired voltage-frequency tradeoff.