Bypassable Clocked Storage for Fixed-Frequency DVFS
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Solution Overview
Problem
Conventional dynamic voltage-frequency scaling (DVFS) schemes in digital integrated circuits are limited by fixed voltage-frequency relationships determined at design time, which restrict the ability to adjust operating frequencies based on changing workload conditions without reconfiguring the circuit, leading to suboptimal power consumption and performance.
Innovation Solution
The integration of programmable logic circuitry with bypassable clocked storage elements and combinational logic delay elements allows for dynamic voltage-frequency scaling by selectively enabling or disabling registers and adjusting power supply voltages and clock frequencies, enabling operation at various voltage-frequency states without reconfiguration, supporting multithreading and feedback loops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the voltage is increased to reduce gate delays and increase clocking frequency, then performance is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic voltage-frequency scaling by making the voltage and frequency settings adjustable at run-time rather than fixed at design time. Control circuitry allows the integrated circuit to transition between different voltage-frequency points based on workload conditions, enabling performance to be optimized when needed while reducing power consumption during lower-demand periods.
Solution Approach 2:
The patent changes the operating parameters (voltage and frequency) of the integrated circuit dynamically. By adjusting these parameters based on current workload requirements, the system can operate at higher voltage-frequency points for improved performance or lower points for reduced power consumption, resolving the contradiction between performance and power usage.
2Ease of manufacture
If the voltage-frequency relationship is fixed at design time based on circuit structure, then manufacturing simplicity is maintained, but adaptability to changing workload conditions deteriorates
Solution Approach 1:
The patent introduces dynamic adjustability to the previously fixed voltage-frequency relationship. Control circuitry is added that allows runtime modification of operating parameters without requiring physical reconfiguration of the circuit structure, maintaining manufacturing simplicity while enabling adaptability to varying workload conditions.
Solution Approach 2:
The patent makes the integrated circuit capable of operating at multiple voltage-frequency points rather than being limited to a single fixed relationship. This multi-functionality allows the same circuit structure to adapt to different workload conditions by switching between operational states, resolving the contradiction between manufacturing simplicity and adaptability.
3Use of energy by moving object
If more bypassable registers are enabled to allow lower voltage operation, then power consumption is reduced, but latency increases
Solution Approach 1:
The patent implements dynamic control of register enabling/disabling based on operational requirements. The control circuitry can adjust the number of active bypassable registers at runtime, allowing the system to optimize between power consumption and latency depending on current workload conditions, rather than having a fixed register configuration.
Solution Approach 2:
The patent selectively enables only the necessary number of bypassable registers required for the current operational mode. Rather than always enabling all registers or none, the control circuitry activates the appropriate subset to achieve the desired balance between power savings and performance, applying partial action to resolve the contradiction.
Data Source
AI summary
Integrated circuits with sequential logic circuitry are provided. Sequential logic circuitry may include a chain of bypassable clocked storage elements coupled between a speed critical input terminal and a speed critical output terminal. Combinational logic circuits may be interposed between each adjacent pair of bypassable clocked storage elements in the chain. Dynamic voltage-frequency scaling (DVFS) control circuitry may provide an adjustable power supply voltage to the combinational logic circuits and may provide an adjustable clock signal to control the clocked storage elements. The DVFS control circuitry may be used to selectively enable at least some of the bypassable clocked storage elements while disabling other bypassable clocked storage elements so that the power supply voltage can be reduced while maintaining the same operating frequency. The power supply voltage and the frequency of the clock signal can be adjusted to provide the desired voltage-frequency tradeoff.