Byte-Addressable Dedicated Memory for Operand Storage
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Solution Overview
Problem
Computer processors face challenges in efficiently managing transient operands due to the limitations of general register machines, including increased complexity, entropy, and power requirements, while alternative architectures like accumulator and stack machines are less efficient for parallel processing.
Innovation Solution
A computer processing system with a first memory structure for temporarily storing operands over multiple cycles and a dedicated byte-addressable memory structure for storing copies of these operands, utilizing a spill unit for context management during CALL, RETURN, and Interrupt operations, and employing a circular buffer with window-based logical-to-physical mapping for efficient operand handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the number of registers is increased to hold more transient operands, then processing speed is improved by avoiding memory access, but instruction entropy and hardware complexity increase
Solution Approach 1:
The patent divides the operand storage system into multiple specialized memory structures (first memory structure for transient operands, second memory structure for spilled operands) rather than using a single general register file. This segmentation allows optimization for different operand lifetimes and access patterns, improving speed while managing complexity through specialized components.
Solution Approach 2:
The patent introduces a spill unit as an intermediary component that manages data transfer between the first memory structure and the second memory structure. This intermediary handles the complexity of operand management, allowing the functional units to access operands efficiently without directly managing the complexity of spilled operands, thus improving processing speed while containing hardware complexity in a dedicated management unit.
2Speed
If the number of registers is increased to hold more transient operands, then processing speed is improved by avoiding memory access, but instruction entropy increases
Solution Approach 1:
The patent segments the address space into different memory structures with different addressing schemes. The first memory structure uses compact addressing for frequently accessed transient operands, while the second memory structure handles spilled operands separately. This segmentation allows instructions to use shorter, more efficient addresses for common operations, reducing instruction entropy while maintaining fast access speed.
3Device complexity
If accumulator machine architecture is used to reduce complexity, then hardware complexity is reduced, but parallel processing efficiency decreases
Solution Approach 1:
The patent creates a universal operand storage system where the first memory structure can serve multiple functional units simultaneously, enabling parallel access. Unlike a single accumulator that serves one function at a time, this multi-functional memory structure supports parallel processing while maintaining relatively simple hardware through shared resources and efficient address routing.
4Device complexity
If stack machine architecture is used to reduce complexity, then hardware complexity is reduced, but parallel processing efficiency decreases
Solution Approach 1:
The patent segments the storage system into multiple independent memory structures rather than using a single LIFO stack. This allows different functional units to access different memory structures or different regions simultaneously, enabling parallel processing while keeping each individual memory structure relatively simple in hardware design.
Data Source
AI summary
A computer processor including a first memory structure that operates over multiple cycles to temporarily store operands referenced by at least one instruction. A plurality of functional units performs operations that produce and access operands stored in the first memory structure. A second memory structure is provided, separate from the first memory structure. The second memory structure is configured as a dedicated memory for storage of operands copied from the first memory structure. The second memory structure is organized with a byte-addressable memory space and each operand stored in the second memory structure is accessed by a given byte address into the byte-addressable memory space.