Byte-Addressable Storage Class Memory Data Access
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The inefficiency of using a page cache for accessing data from Storage Class Memories (SCMs) due to their faster access times, which are not fully utilized because of fixed block or page sizes, leading to increased processing overhead and latency when accessing data from Data Storage Devices (DSDs).
Innovation Solution
Implementing a byte-addressable Storage Class Memory (SCM) that allows direct access and caching of data at a granular level, eliminating the need for a page cache in the host's main memory by using unique identifiers for data stored in secondary memory and enabling delta-encoding techniques for reduced data transfer, thereby optimizing data access and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a page cache is used in DRAM main memory to access data from conventional secondary memory, then data access speed is improved, but device complexity and power consumption increase due to maintaining and operating the page cache
Solution Approach 1:
The patent extracts the caching function from the host's DRAM main memory and relocates it directly into the SCM device. The SCM controller manages a cache within the SCM namespace, eliminating the need for a separate page cache in host memory. This reduces device complexity at the host side while maintaining fast data access through the embedded cache in SCM.
Solution Approach 2:
The SCM acts as an intermediary between the host and conventional secondary memory. By implementing caching within the SCM device itself, it mediates data access requests, providing fast access to frequently used data without requiring the host to maintain a separate page cache in DRAM, thus reducing overall system complexity.
2Speed
If a page cache is used in DRAM main memory to access data from SCM, then data access speed is improved, but the faster access times of SCM are not fully utilized due to fixed block or page size processing overhead
Solution Approach 1:
The patent segments the SCM namespace into cache and non-cache portions, allowing fine-grained control over which data resides in the fast SCM cache versus conventional secondary memory. This segmentation enables byte-addressable access to cached data without the fixed block size constraints of traditional page caches, reducing processing overhead and fully utilizing SCM's fast access times.
Solution Approach 2:
The patent implements dynamic caching where the SCM controller can flexibly manage which data is cached in the SCM namespace based on access patterns. This dynamic approach allows the system to adapt to varying data access requirements, optimizing performance by keeping frequently accessed data in the fast SCM cache while avoiding the rigid fixed block size limitations of conventional page caches.
3Device complexity
If fixed block or page size is used for data access in SCM, then data access structure is simplified, but processing overhead increases and latency increases despite faster SCM access times
Solution Approach 1:
The patent segments the SCM namespace into cache and non-cache portions, enabling byte-addressable access to cached data. This segmentation allows the system to maintain a simple access structure for cached data while avoiding the processing overhead associated with fixed block or page size operations, thereby reducing latency and fully utilizing SCM's fast access capabilities.
4Device complexity
If data is accessed from SCM using fixed block or page size, then data transfer is simplified, but data transfer volume increases and power consumption increases
Solution Approach 1:
The patent segments the SCM namespace into cache and non-cache portions, enabling precise control over which data is transferred between SCM and conventional secondary memory. This segmentation allows the system to transfer only the necessary amount of data at byte-addressable granularity rather than transferring entire fixed-size blocks or pages, reducing data transfer volume and associated power consumption while maintaining simplified transfer processes.
Data Source
AI summary
A device includes a Storage Class Memory (SCM) and a secondary memory with at least one of a greater read or write latency than the SCM. At least a portion of the SCM is provided as an address space of a processor. An SCM smallest writable unit for writing data in the SCM is smaller than a secondary memory smallest writable unit for writing data in the secondary memory. An operation instruction is received from the processor to perform an operation on data stored in the secondary memory. The data is loaded from the secondary memory into the SCM for performance of the operation.