Bytecode Accelerator Handover via Dedicated Bus
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Solution Overview
Problem
Existing microprocessors face inefficiencies in switching between hardware and software processing modes due to limited data transfer capabilities on dedicated buses, which hinders high-speed operation when translating bytecodes into native instructions.
Innovation Solution
Incorporating a selection control circuit that manages data transfer on a dedicated bus to selectively output and input multiple pieces of internal information, including register management and event count data, allowing for high-speed sharing between hardware and software processing modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a dedicated bus is used to transfer data between hardware accelerator and CPU register file upon mode switching, then data transfer speed is improved, but the amount of data that can be transferred is limited to one data at a time
Solution Approach 1:
The data transfer process is segmented into multiple phases: saving internal information from hardware accelerator to CPU, switching to software mode, executing software processing, then switching back to hardware mode and restoring internal information. This segmentation allows the system to handle multiple data items sequentially through the dedicated bus, overcoming the limitation of single-data transfer while maintaining high transfer speeds for each item.
Solution Approach 2:
The system performs preliminary actions by saving internal information (such as program counter, stack pointer, and register states) from the hardware accelerator to the CPU register file before mode switching occurs. This preliminary saving ensures that when switching back to hardware mode, the internal information can be quickly restored without delay, effectively preparing the system for rapid mode transitions.
2Adaptability or versatility
If hardware processing and software processing are switched with high frequency, then processing flexibility is improved, but switching overhead increases
Solution Approach 1:
The hardware accelerator is designed to autonomously manage its own internal information (program counter, stack pointer, register states) and automatically save/restore this information during mode switching. This self-service capability eliminates the need for complex external control logic and reduces switching overhead, allowing frequent transitions between hardware and software modes without significant time loss.
Solution Approach 2:
The dedicated bus is designed to serve multiple functions: transferring internal information during mode switching, transferring data during normal operation, and supporting both hardware and software processing modes. This multi-functionality reduces the need for separate dedicated pathways for different operations, simplifying the overall system architecture and reducing switching overhead.
Data Source
AI summary
A bytecode accelerator which translates stack-based intermediate language (bytecodes) into register-based CPU instructions transfers plural pieces of internal information from a register file of a CPU to the bytecode accelerator by means of an internal transfer bus between the bytecode accelerator and the CPU and an input selection logic of the bytecode accelerator when the bytecode accelerator is started and transfers plural pieces of internal information in the bytecode accelerator to the register file of the CPU by means of the internal transfer bus, an output selector and an output selector selection logic of the bytecode accelerator when the bytecode accelerator ends its operation in transition between hardware processing and software processing by software virtual machine.