Bytecode Interpreter Register Pre-fetching for Execution Speed
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Solution Overview
Problem
The existing virtual machine (VM) interpreter for bytecode instruction streams is inefficient due to the time-consuming process of querying instruction sequence and mapping tables, which affects the overall system performance, especially in blockchain applications where speed is critical.
Innovation Solution
The method involves pre-obtaining and storing the function address of subsequent instructions in a register, allowing direct access and reducing the need for frequent memory queries, thereby accelerating the execution of bytecode instruction streams.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the interpreter queries instruction sequence and mapping tables from memory for each bytecode instruction, then the execution is accurate and complete, but the execution speed is slow due to frequent memory access
Solution Approach 1:
The patent pre-loads instruction sequence tables and mapping tables from memory into cache before execution, and pre-fetches subsequent instruction addresses into registers during instruction execution. This preliminary action reduces the need for frequent memory access during runtime, directly addressing the contradiction between execution completeness and speed by preparing data in advance in faster storage locations.
Solution Approach 2:
The patent introduces cache and registers as intermediary storage between memory and the instruction execution unit. Instead of directly accessing memory for every instruction, the system uses cache as a buffer layer and registers for immediate data, reducing memory access frequency and improving execution speed while maintaining accuracy through proper data management.
2Productivity
If the interpreter accesses memory frequently to retrieve instruction addresses and mapping information, then data accuracy is maintained, but system performance deteriorates
Solution Approach 1:
The system performs preliminary loading of instruction sequence tables and mapping tables into cache memory before bytecode execution begins. Additionally, during instruction execution, the next instruction address is pre-fetched and stored in registers in advance. This preliminary preparation reduces the frequency of cache and memory access during execution, improving system performance while maintaining data accuracy.
Solution Approach 2:
The patent creates copies of frequently accessed data structures (instruction sequence tables, mapping tables) and stores them in cache memory. This copying approach allows the system to access data from the faster cache rather than repeatedly accessing the slower main memory, thereby improving productivity while maintaining data integrity through proper synchronization.
3Productivity
If the interpreter uses a straightforward approach to decode and execute each bytecode instruction sequentially, then the implementation is simple, but the execution efficiency is low
Solution Approach 1:
The patent implements pre-fetching of subsequent instruction addresses into registers during the execution of current instructions. This preliminary action allows the interpreter to prepare data for the next instruction in advance, enabling more efficient pipeline execution without significantly increasing the complexity of the interpreter structure. The pre-computation of next instruction addresses reduces wait time and improves throughput.
Data Source
AI summary
Implementations of the present specification are provided for interpreting a bytecode instruction stream. An interpreter of a virtual machine receives an instruction stream comprising a plurality of machine instructions. A first value, comprising a current analog function address and stored in a first register corresponding to a current instruction of the plurality of machine instructions, is read. The validity of the first value is determined. If the first value is valid, the first value is stored in a second register configured to store current analog function addresses corresponding to current instructions in the instruction stream. A subsequent analog function address corresponding to a subsequent instruction associated with the current instruction is retrieved by using the current analog function address. The subsequent analog function address is stored in the first register. The current instruction is executed based on the current analog function address read from the second register.