Bytecode Execution Optimization via Automatic ISA Detection

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In systems that execute bytecode, a just-in-time compiler cannot generate optimal native code for an extended instruction set architecture (ISA) supported by the CPU unless the extended ISA is manually designated in the command line argument, leading to suboptimal performance.

Innovation Solution

A computer system that automatically includes a command line argument for optimizing native code generation by using a correspondence table to associate the extended ISA with the necessary command line argument, allowing the CPU to acquire and set the argument during bytecode execution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the extended ISA is manually designated in the command line argument, then optimal native code generation is achieved, but user operation complexity increases and automation is reduced

Engineering Contradiction:
Improvenative code generation optimizationVSAvoidmanual command line argument setting
Core Design Contradiction:
ProductivityVSEase of operation

Solution Approach 1:

The system automatically detects the CPU's extended ISA capabilities and selects appropriate command line arguments without user intervention. The Java virtual machine calling unit queries the CPU ID register to identify supported extensions and autonomously configures the optimization flags, enabling the system to serve itself rather than requiring manual configuration.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system performs preliminary detection of CPU capabilities before bytecode execution. By querying the CPU ID register in advance and storing the capability information, the system prepares the necessary command line arguments beforehand, ensuring optimal native code generation is enabled from the start without requiring user input during execution.

Inventive Principle:
Principle #10Preliminary action

2Ease of operation

If the extended ISA is not designated in the command line argument, then ease of operation is maintained, but native code generation optimization is lost

Engineering Contradiction:
Improveautomatic execution without manual settingVSAvoidnative code generation optimization
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The system implements a feedback mechanism where the Java virtual machine calling unit continuously monitors CPU capability information from the ID register and adjusts command line arguments accordingly. This feedback loop ensures that the system automatically adapts to the actual CPU capabilities, maintaining both ease of operation and optimization performance.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The invention introduces an intermediary component (the Java virtual machine calling unit with correspondence table) that bridges the gap between CPU capabilities and command line arguments. This intermediary automatically translates CPU ID register information into appropriate optimization flags, eliminating the need for user intervention while ensuring proper configuration.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Extent of automation

If a correspondence table is introduced to map extended ISA to command line arguments, then automation is improved, but device complexity increases

Engineering Contradiction:
Improveautomatic command line argument settingVSAvoidcorrespondence table structure
Core Design Contradiction:
Extent of automationVSDevice complexity

Solution Approach 1:

The correspondence table is pre-populated with mappings between extended ISA types and their associated command line arguments during system initialization or compilation. This preliminary preparation allows the runtime system to simply lookup and apply the appropriate arguments without complex decision logic, reducing runtime complexity while maintaining high automation.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20240281269A1Computer and method
Publication Date: 2024.08.22 TOSHIBA TEC KK
  • US20240281269A1 patent drawing
  • US20240281269A1 patent drawing
  • US20240281269A1 patent drawing

AI summary

According to one embodiment, a computer includes a CPU and a storage device. The storage device stores an operating system that executes a bytecode without optimization for an extended ISA supported by the CPU unless the extended ISA is designated in a command line argument for executing the bytecode. The storage device further stores a correspondence table showing a correspondence between a value of an extension field indicating the extended ISA and the command line argument enabling optimization corresponding to the extended ISA. A program in the storage device is configured to cause the CPU to acquire an ISA supported by the CPU, acquire the extended ISA from the ISA, refer to the correspondence table to acquire the command line argument associated with the extended ISA, and then automatically include the command line argument associated with the extended ISA when executing the bytecode.