Bytewise Shifting Redundancy for Memory Reliability
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Solution Overview
Problem
Computing systems face challenges in increasing the reliability of memory accesses due to the limited on-die area for memory arrays in mobile devices, transistor variations leading to faulty bit cells, and the need for efficient power consumption and noise sensitivity, which existing technologies have not adequately addressed.
Innovation Solution
The implementation of a redundancy logic system that shifts write data and write mask data towards neighboring columns with functioning bit cells, using redundant columns to replace failing ones, and only shifting a subset of write mask bits to reduce routing and circuitry, thereby maintaining data consistency and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory array size is increased to store more data and instructions, then the storage capacity is improved, but the probability of faulty bit cells increases due to more transistors and fabrication variations
Solution Approach 1:
The patent applies preliminary action by pre-configuring redundant columns alongside the main memory array during fabrication. These redundant columns are prepared in advance and can be quickly activated through column decoder redirection when failures are detected, preventing the need to redesign or replace the entire memory array.
Solution Approach 2:
The patent changes the operational parameters of the memory system by dynamically redirecting column decoder outputs to alternative redundant columns when bit cell failures are detected. This parameter change allows the same physical hardware to operate in different configurations, maintaining reliability as the array size increases.
2Reliability
If redundant columns are added to replace failing bit cells, then the reliability is improved, but the on-die area consumption increases
Solution Approach 1:
The patent applies partial action by implementing redundancy only for specific columns that are prone to failures or have already failed, rather than duplicating the entire memory array. The redundant columns are strategically placed and activated only when needed, providing reliability improvement with minimal area overhead.
Solution Approach 2:
The redundant columns serve multiple functions: they can replace failed columns, provide additional storage capacity, and offer backup pathways for data access. This multi-functionality allows the same redundant structure to address multiple potential failure modes without proportionally increasing area consumption.
3Reliability
If write data and write mask data are shifted to neighboring columns to replace failing columns, then the reliability is improved, but the routing complexity and circuitry increase
Solution Approach 1:
The patent segments the write data and write mask data into separate handling paths, with specific logic for detecting failures and redirecting only the necessary data segments to redundant columns. This segmentation allows the shifting operation to be performed in a structured, modular manner, reducing overall routing complexity.
Solution Approach 2:
The patent introduces intermediary logic circuits that mediate between the write data input and the column decoders. These intermediaries handle the shifting and redirection operations, isolating the complexity from the main data path and making the routing more manageable and systematic.
Data Source
AI summary
Systems, apparatuses, and methods for efficiently increasing reliability of memory accesses are described. In various embodiments, write data and write mask data are shifted by redundancy logic in a memory. The redundancy logic receives write data bits, which are segmented into one or more write groups in addition to one or more mask bits and one or more shift bits per write group. If the redundancy logic detects a first shift bit assigned to a first write group is asserted, then the redundancy logic selects a second mask bit assigned to a second write group different from the first write group. Otherwise, a first mask bit assigned to the first write group is selected. Following, the redundancy logic combines the selected mask bit with the first data bit of the first write group.