C-PHY Clock Recovery with Multi-Stage Unit Interval Detection
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Solution Overview
Problem
The increasing frequency range in C-PHY protocols necessitates a larger number of delay units in receivers, leading to increased size and costs, as existing methods struggle to efficiently recover clock signals with a reduced number of delay units.
Innovation Solution
An electronic device employing a multi-stage unit interval detector with a decreased total delay amount, utilizing a combination of delay cells and feedback loops to perform coarse and fine detection, allowing for clock signal recovery with fewer delay units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of delay units is increased to support higher frequency ranges, then clock signal recovery capability is improved, but device size and cost increase
Solution Approach 1:
The patent divides the delay loop into multiple stages (first delay loop, second delay loop, third delay loop) with different delay amounts. Each stage handles a specific range of delay requirements, allowing the system to cover the full frequency range without needing a single large number of delay units. This segmentation reduces the total number of delay units while maintaining clock recovery capability across all frequency ranges.
Solution Approach 2:
The patent implements dynamic selection of delay loops based on the detected frequency range. The system adaptively activates only the necessary delay loops (first, second, or third) depending on whether the input signal is in the first, second, or third frequency range. This dynamic approach ensures optimal performance with minimal resource usage, avoiding the need to provision for the maximum possible frequency range at all times.
2Device complexity
If the total delay amount of delay cells is reduced, then device size is decreased, but clock signal recovery precision may be compromised
Solution Approach 1:
The patent segments the delay measurement function across three different delay loops, each optimized for a specific frequency range. The first delay loop handles the first frequency range with its delay amount, the second delay loop handles the second frequency range, and the third delay loop handles the third frequency range. This segmentation allows each loop to be precisely tuned for its specific range, maintaining high measurement precision while keeping individual loop delay amounts small.
Solution Approach 2:
The patent changes the delay parameter (delay amount) of different delay loops to match different frequency ranges. Each delay loop is configured with a specific delay amount suitable for its target frequency range, allowing the system to maintain optimal precision across all frequencies without requiring a single large delay amount that would compromise device size.
Data Source
AI summary
An electronic device includes a unit interval detector including a plurality of delay cells and that receives a first signal, a second signal, and a third signal and detects a code indicating a unit interval from the first signal, the second signal, and the third signal, a clock recovery circuit that generates a clock signal from the first signal, the second signal, and the third signal in response to the code, and a data recovery circuit that generates a first receive signal, a second receive signal, and a third receive signal from the first signal, the second signal, and the third signal in response to the code and the clock signal. A total delay amount of the delay cells is smaller than a length of the unit interval and the unit interval detector performs a multi-stage detection operation including coarse detection and fine detection by using the delay cells.