C-PHY Receiver Architecture With Low-Speed Symbol Decoding
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Solution Overview
Problem
C-PHY receivers for MIPI communication face challenges in full-rate operation and exhibit low efficiency due to difficulties in designing symbol decoders and de-mappers, which are typically inefficient and complex, necessitating a semi-custom design approach.
Innovation Solution
The proposed receiver includes an input buffer, de-serializer, D flip-flop, symbol decoder, and de-mapper, driven at reduced speeds to enable semi-custom design, allowing for efficient operation and reduced power consumption and circuit complexity by operating the symbol decoder and de-mapper at lower speeds through coding in Verilog.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a full-custom design is used for the C-PHY receiver, then the operation speed can be maximized, but the design complexity and difficulty increase significantly due to the need to design symbol decoders and de-mappers according to MIPI physical layer specifications
Solution Approach 1:
The receiver is divided into two distinct parts: a full-custom designed high-speed interface layer (input buffer, de-serializer) and a semi-custom designed protocol processing layer (symbol decoder, de-mapper). This segmentation allows the speed-critical components to be optimized for maximum performance while the specification-constrained components can be developed using standardized semi-custom methodologies, thereby resolving the contradiction between speed and design complexity.
2Ease of manufacture
If a semi-custom design is used for the symbol decoder and de-mapper, then the ease of manufacture and design efficiency improve, but the operation speed decreases due to the divided clock rate
Solution Approach 1:
The system dynamically adapts the clock rate for different operational stages: the full-rate clock is used for high-speed signal reception and de-serialization, while a divided clock rate is applied to the symbol decoder and de-mapper during protocol processing. This dynamic clock management enables semi-custom design implementation while minimizing the impact on overall system speed, as the speed-critical path operates at full rate.
3Productivity
If the symbol decoder and de-mapper are designed to operate at full rate, then the productivity and throughput are maximized, but the power consumption and circuit complexity increase significantly
Solution Approach 1:
The symbol decoder and de-mapper operate periodically at a divided clock rate rather than continuously at full rate. The de-serializer operates at full rate to maintain throughput, while the symbol decoder and de-mapper process data at lower speed intervals, reducing their power consumption and circuit complexity requirements while maintaining overall system productivity through efficient pipelining.
Data Source
AI summary
A receiver for data communication may include: an input buffer suitable for generating plural comparison signals by differentially comparing plural input signals; a de-serializer suitable for generating plural groups of de-serialized signals by de-serializing the plural comparison signals at a preset de-serialization ratio; a D flip-flop suitable for generating plural delayed signals by delaying last de-serialized signals of the respective plural groups of de-serialized signals by a preset time; a symbol decoder suitable for comparing current and previous states of the plural comparison signals and for generating plural symbol signals based on a preset state diagram defining a correspondence relationship between the plural symbol signals and changes between current and previous states of the plural comparison signals.