C-PHY Receiver Skew Calibration Using Embedded Clock Recovery
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Solution Overview
Problem
C-PHY protocol receivers face challenges in calibrating skew between data and clock signals due to the absence of a separate clock signal, which affects the recovery of accurate clock and data signals.
Innovation Solution
An electronic device with processing circuitry that receives signals from multiple signal lines, calculates differences, adjusts delay amounts, generates pulse signals, detects unit intervals, and performs skew calibration to recover the clock signal and data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a separate clock signal is not exchanged between devices (C-PHY protocol), then the protocol achieves higher integration and fewer signal lines, but the receiver fails to calibrate skew between data and clock signals
Solution Approach 1:
The patent merges the clock signal with data signals to form combined signals that are transmitted through the same channel. The receiver then separates and recovers the clock signal from these combined signals, eliminating the need for separate clock signal lines while maintaining skew calibration capability through the embedded clock information
Solution Approach 2:
The patent introduces combined signals as an intermediary that carries both data and clock information together. This intermediary structure allows the receiver to access embedded clock information for skew calibration without requiring separate clock signal lines, thus resolving the contradiction between signal line reduction and calibration accuracy
2Device complexity
If the receiver recovers clock signal from embedded clock in combined signals, then separate clock signal lines are eliminated, but skew calibration becomes more difficult without separate clock signal
Solution Approach 1:
The patent implements a self-service mechanism where the receiver uses the embedded clock information within the combined signals itself to perform skew calibration. The system calibrates itself by comparing transition timings of the combined signals without requiring external separate clock signals, thus reducing calibration difficulty despite the integrated signal structure
Solution Approach 2:
The patent employs feedback mechanisms where the receiver detects skew in the combined signals, adjusts its internal timing accordingly, and iteratively refines the skew calibration. This feedback loop enables automatic calibration using only the embedded clock information from the combined signals, making the process manageable despite the integrated structure
Data Source
AI summary
An electronic device includes processing circuitry outputting first to third signals, delaying first to third signals to output fourth to sixth signals, generating a pulse signal based on the fourth signal, the fifth signal, and the sixth signal, detecting lengths of intervals, and adjusting at least one of a first code, a second code, and a third code based on fourth codes.