Conductive C-Plane GaN Substrate With Uniform Crystallinity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current C-plane GaN substrates for nitride semiconductor devices face challenges in achieving optimal crystallinity and electrical properties, particularly in terms of resistivity and carrier concentration, which affect their performance and reliability.
Innovation Solution
A conductive C-plane GaN substrate with specific electrical properties and crystallinity conditions is developed, including a resistivity of 2×10−2 Ω·cm or less and an n-type carrier concentration of 1×10^18 cm−3 or more, with controlled XRC-FWHMs and peak angle variations, and the presence of dislocation arrays, to enhance its suitability for nitride semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional C-plane GaN substrates are used for nitride semiconductor devices, then manufacturing simplicity is maintained, but electrical properties (resistivity and carrier concentration) are insufficient
Solution Approach 1:
The patent applies parameter changes by precisely controlling the resistivity (2×10^-2 Ω·cm or less) and n-type carrier concentration (1×10^18 cm^-3 or more) of the C-plane GaN substrate. These parameter specifications transform the substrate from conventional insufficient electrical properties to optimized conductive state, directly resolving the contradiction between maintaining manufacturing simplicity and achieving reliable electrical properties.
2Reliability
If standard GaN crystal growth methods are used, then manufacturing simplicity is maintained, but crystallinity quality is insufficient
Solution Approach 1:
The patent replaces conventional mechanical crystal growth methods with a chemically optimized growth process that achieves superior crystallinity. By substituting the growth mechanism with chemically controlled processes (indicated by the specific XRC-FWHM values and dislocation array characteristics), the patent achieves high crystallinity quality without proportionally increasing process complexity.
3Reliability
If high carrier concentration is achieved through doping, then electrical conductivity is improved, but crystal defects increase
Solution Approach 1:
The patent changes the fundamental parameter approach by achieving high n-type carrier concentration (1×10^18 cm^-3 or more) through substrate optimization rather than heavy doping. This parameter transformation maintains electrical conductivity while avoiding the crystal defects that typically accompany high-level doping, thus resolving the contradiction between conductivity improvement and crystal quality preservation.
Data Source
AI summary
A conductive C-plane GaN substrate has a resistivity of 2×10−2 Ω·cm or less or an n-type carrier concentration of 1×1018 cm−3 or more at room temperature. At least one virtual line segment with a length of 40 mm can be drawn at least on one main surface of the substrate. The line segment satisfies at least one of the following conditions (A1) and (B1): (A1) when an XRC of (004) reflection is measured at 1 mm intervals on the line segment, a maximum value of XRC-FWHMs across all measurement points is less than 30 arcsec; and (B1) when an XRC of the (004) reflection is measured at 1 mm intervals on the line segment, a difference between maximum and minimum values of XRC peak angles across all the measurement points is less than 0.2°.