C-Shaped Resistor for 3D Memory Lamination
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Solution Overview
Problem
The manufacturing process of 3-dimensional nonvolatile memory devices is complicated and costly due to the need for a separate process to form resistors with a single-layered structure, unlike the laminated memory cells.
Innovation Solution
A resistor structure is created using a first conductive layer, a second conductive layer protruding from the first, and a third conductive layer electrically coupled to the second, with contact plugs, allowing for a simplified manufacturing process by integrating resistor formation with memory cell lamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single-layered resistor structure is used, then the resistor can be formed with a simple structure, but the manufacturing process becomes complicated and costs increase due to needing an additional separate process
Solution Approach 1:
The patent merges the resistor formation process with the memory cell lamination process by forming resistors using the same stacked conductive layers (first, second, and third conductive layers) that constitute the memory cells. This integration eliminates the need for a separate resistor fabrication process, directly resolving the contradiction between simple resistor structure and complicated manufacturing process.
Solution Approach 2:
The stacked conductive layers are designed to serve dual purposes: they form both the memory cell structure and the resistor structure. The first conductive layer, second conductive layer, and third conductive layer collectively function as both memory cell components and resistor components, allowing one structure to fulfill multiple functions and eliminating redundant manufacturing steps.
2Device complexity
If a single-layered resistor structure is used, then the resistor structure is simple, but manufacturing costs increase due to additional processes
Solution Approach 1:
The patent merges the resistor formation process with the memory cell lamination process by forming resistors using the same stacked conductive layers (first, second, and third conductive layers) that constitute the memory cells. This integration eliminates the need for a separate resistor fabrication process, directly resolving the contradiction between simple resistor structure and complicated manufacturing process.
Solution Approach 2:
The stacked conductive layers are designed to serve dual purposes: they form both the memory cell structure and the resistor structure. The first conductive layer, second conductive layer, and third conductive layer collectively function as both memory cell components and resistor components, allowing one structure to fulfill multiple functions and eliminating redundant manufacturing steps.
3Productivity
If memory cells are laminated in a 3-dimensional structure, then the degree of integration is improved, but the resistor formation requires an additional separate process
Solution Approach 1:
The patent merges the resistor formation process with the memory cell lamination process by forming resistors using the same stacked conductive layers (first, second, and third conductive layers) that constitute the memory cells. This integration eliminates the need for a separate resistor fabrication process, directly resolving the contradiction between simple resistor structure and complicated manufacturing process.
Data Source
AI summary
A resistor includes a first conductive layer; a second conductive layer protruding from the first conductive layer; a third conductive layer located above and facing the first conductive layer to face the first conductive layer; and at least two contact plugs electrically coupled to the third conductive layer.