Multi-Gate Transistor Spacer Geometry for Leakage and Capacitance
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Solution Overview
Problem
Conventional multi-gate transistors, such as MBC transistors, face issues with insufficient spacing between the gate structure and the epitaxial source/drain feature, leading to leaks and increased parasitic capacitance due to inadequate inner spacer features.
Innovation Solution
The implementation of inner spacer features with a convex or C-shape design, where the gate dielectric layer extends partially between the channel member and the inner spacer feature, ensuring sufficient separation and reducing leakage and parasitic capacitance by preventing the gate electrode from intruding between the connection portion and the inner spacer feature.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional inner spacer features are used in MBC transistors, then the gate structure can be positioned relative to the epitaxial source/drain feature, but the spacing is insufficient leading to leaks and increased parasitic capacitance
Solution Approach 1:
The inner spacer feature is designed with a convex shape that curves toward the gate structure, creating a C-shaped configuration when viewed along the channel length. This curved geometry provides enhanced spacing between the gate structure and epitaxial source/drain feature, effectively reducing leakage and parasitic capacitance while maintaining manufacturability through standard deposition and etching processes.
2Reliability
If the gate electrode is allowed to extend fully around the channel region, then gate control is maximized, but the gate electrode may intrude between the connection portion and inner spacer feature causing leaks
Solution Approach 1:
The gate electrode is designed with varying extent of wraparound: in first regions adjacent to inner spacer features, the gate electrode extends only partially around the channel region to prevent intrusion and leakage, while in second regions between inner spacer features, the gate electrode extends fully around the channel region to maximize gate control. This spatially differentiated design optimizes both reliability and ease of operation.
3Object-generated harmful factors
If inner spacer features are implemented to increase spacing, then leakage and parasitic capacitance are reduced, but the manufacturing process becomes more complex
Solution Approach 1:
The inner spacer feature is formed as a preliminary structure before the gate electrode is deposited. By pre-forming the convex-shaped spacer with the C-shaped configuration, the subsequent gate electrode deposition and patterning processes are simplified, as the spacer already defines the required spacing and prevents gate electrode intrusion, thereby reducing overall manufacturing complexity despite the additional initial step.
Data Source
AI summary
A semiconductor device according to the present disclosure includes a first channel member including a first channel portion and a first connection portion, a second channel member including a second channel portion and a second connection portion, a gate structure disposed around the first channel portion and the second channel portion, and an inner spacer feature disposed between the first connection portion and the second connection portion. The gate structure includes a gate dielectric layer and a gate electrode. The gate dielectric layer extends partially between the inner spacer feature and the first connection portion and between the inner spacer feature and the second connection portion. The gate electrode does not extend between the inner spacer feature and the first connection portion and between the inner spacer feature and the second connection portion.