CA-Based Decompression Circuit for Parallel IC Test Signal Expansion
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Solution Overview
Problem
The challenge of testing integrated circuit (IC) chips is the high cost and time consumption due to the limited number of input and output pins, necessitating serial input of large quantities of test stimuli and comparison of test results, which is inefficient and costly with current automatic test equipment (ATE).
Innovation Solution
A decompression circuit utilizing cellular automaton (CA) circuits and phase shifters to expand test stimuli into a large quantity of scan chain signals, allowing efficient testing of IC components through a few input pins, with randomness implemented via CA circuits and expansion via phase shifters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a large quantity of test stimuli are input in serial mode through limited input pins, then the number of testable components increases, but the test time increases significantly
Solution Approach 1:
The decompression circuit is divided into multiple sub-circuits, each containing multiple CA circuits and a phase shifter. This segmentation allows parallel processing of test stimuli, where each sub-circuit can independently generate and output test signals through different scan chains, thereby increasing the number of testable components without proportionally increasing test time
Solution Approach 2:
The patent transitions from serial input (one-dimensional) to parallel output through multiple scan chains (multi-dimensional). By using multiple phase shifters that can operate simultaneously with different phase shifts, the system outputs test signals through multiple dimensions (scan chains) rather than sequentially through a single channel, resolving the time-component quantity contradiction
2Productivity
If test stimuli are expanded through multiple scan chains, then test efficiency improves, but the complexity of the decompression circuit increases
Solution Approach 1:
The decompression circuit employs a nested structure where multiple CA circuits are nested within sub-circuits, and multiple sub-circuits are nested within the overall decompression circuit. Each level of nesting reuses the same basic building blocks (CA circuits and phase shifters), which reduces the overall complexity compared to implementing each function separately. The nested architecture allows systematic expansion of test efficiency while controlling complexity through modular repetition
Solution Approach 2:
The patent uses identical copies of CA circuits and phase shifters across multiple sub-circuits. Instead of designing complex unique circuits for each scan chain, the same standardized blocks are copied and configured with different parameters (such as phase shifts). This copying approach improves test efficiency through parallelism while keeping the design complexity manageable through reuse of proven modules
Data Source
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AI summary
This application relates to the field of IC chip testing, and provides a decompression circuit, a circuit generation method, and an IC chip, to test a component in the IC chip by outputting a large quantity of test signals through the decompression circuit. The decompression circuit (12) includes a plurality of sub-circuits (30). The sub-circuit (30) includes a plurality of cellular automaton CA circuits (301) and a phase shifter (302). The CA circuit (301) includes a first XOR circuit (XOR1) and a register (R). The first XOR circuit (XOR1) includes a first input end. A data input end of the register (R) is coupled to an output end of the first XOR circuit (XOR1). A data output end of the register (R) is coupled to the first input end of the first XOR circuit (XOR1) and an input end of the phase shifter (302). The data output end of the register (R) is further coupled to a second input end of a first XOR circuit (XOR1) in at least one other CA circuit (301). The phase shifter (302) is configured to output a test signal.