CLAT Aware Affinity Scheduler for Multi-Core Packet Processing
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Solution Overview
Problem
The transition from IPv4 to IPv6 in CLAT (Customer side translator) results in double processing of data packets, impacting the throughput of user equipment due to multi-level data processing and CPU/system unaware scheduling.
Innovation Solution
A method for CLAT Aware Affinity (CAA)-based scheduling in a multi-core processor, where a CAA scheduler determines the path characteristic of packets, classifies them into high, intermediate, or low priority queues based on IP headers, and schedules them on appropriate cores to optimize connections to IPv4 or IPv6 servers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If CLAT (Customer side translator) is used for IPv4 to IPv6 transition, then IPv6 connectivity is achieved, but data packets undergo double processing which reduces throughput
Solution Approach 1:
The patent segments data packets into different classes (Class A, B, C) based on their IP headers and processing requirements. Class A packets (IPv4 to IPv6 translation needed) are handled separately from Class B (IPv6 native) and Class C (IPv4 direct) packets. This segmentation allows the system to optimize processing paths for each class, avoiding unnecessary double processing for packets that don't require translation, thereby maintaining throughput while achieving IPv6 connectivity.
Solution Approach 2:
The patent applies different processing qualities to different packet classes. For Class A packets requiring translation, full CLAT processing is applied. For Class B and C packets, optimized paths are used that avoid redundant processing. The CAA scheduler assigns different CPU core affinities and priority levels to different packet classes, ensuring that each packet receives the appropriate level of processing attention locally, thus preventing universal double processing and maintaining high throughput.
2Reliability
If multi-level data processing is performed in CLAT, then address translation is achieved, but power consumption increases
Solution Approach 1:
The patent implements dynamic packet classification and scheduling where the CAA scheduler continuously monitors packet characteristics and dynamically assigns them to appropriate CPU cores and priority queues. This dynamic approach ensures that address translation (Class A packets) is performed only when necessary, while other packets are routed through more energy-efficient paths. The system adapts its processing level based on real-time packet requirements, avoiding unnecessary multi-level processing and reducing overall power consumption while maintaining reliable address translation functionality.
Solution Approach 2:
The patent changes the processing parameters (priority level, CPU core affinity, queue assignment) based on packet classification. By modifying these parameters dynamically according to packet type, the system optimizes the balance between performing necessary address translation and minimizing energy consumption. Class A packets receive full translation processing with appropriate priority, while Class B and C packets are handled with optimized parameters that reduce processing overhead and power usage.
3Device complexity
If CPU/system unaware scheduling is used, then system simplicity is maintained, but throughput is reduced
Solution Approach 1:
The patent implements preliminary packet classification based on IP header analysis before scheduling decisions are made. The CAA scheduler pre-categorizes packets into Class A, B, or C based on their source and destination addresses, allowing subsequent scheduling to be performed efficiently without complex runtime analysis. This preliminary action enables the system to maintain relative simplicity while achieving high throughput through optimized core assignment and priority queuing for each packet class.
Solution Approach 2:
The patent introduces the CAA (Connection and Class Aware Affinity) scheduler as an intermediary component between packet reception and processing. This intermediary performs intelligent classification and scheduling based on packet characteristics, CPU core affinities, and system load conditions. By placing this smart intermediary in the data path, the system achieves high throughput through optimized scheduling without requiring complex modifications to the underlying CPU architecture or operating system scheduling mechanisms.
Data Source
AI summary
Embodiments herein provide a method for CLAT Aware Affinity (CAA)-based scheduling by a user equipment (UE) (100) comprising a multi-core processor (120). The method includes a CAA scheduler (180) at the user equipment (100) receiving a packet and determining a path characteristic of the packet. Further, the method includes the CAA scheduler (180) determining, at least one of a IPv4 connection and a IPv6 connection based the path characteristic of the packet; and establishing a connection to at least one of an IPv4 server and an IPv6 server based on the determined at least one of the IPv4 connection and the IPv6 connection. Further, the method includes the CAA scheduler (180) classifying the packet into at least one class and scheduling the packet on at least one core of the multi-core processor (120) based on the at least one class.