CAAC Oxide Semiconductor Channel Layout for Short-Channel Stability
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Solution Overview
Problem
Miniaturization of transistors with oxide semiconductors leads to fluctuations in electric characteristics due to short-channel effects, particularly when the channel length is shortened, and existing plasma treatment methods can cause etching issues and increase resistance in thin oxide semiconductor layers.
Innovation Solution
A semiconductor device with a CAAC oxide semiconductor channel formation region and amorphous regions with varying dopant concentrations, where the dopant concentration is higher in the regions adjacent to the channel, helps relieve the electric field applied to the channel, reducing short-channel effects and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the channel length is shortened for miniaturization, then the transistor size is reduced, but the electric characteristics fluctuate due to short-channel effects
Solution Approach 1:
The patent applies local quality by creating regions with different dopant concentrations within the oxide semiconductor layer. Specifically, highly doped regions are formed adjacent to the source and drain electrodes, while the channel region maintains a lower dopant concentration. This spatial variation in dopant concentration allows the transistor to achieve miniaturization while maintaining stable electric characteristics, as the highly doped regions compensate for short-channel effects without degrading the channel quality.
2Reliability
If argon plasma treatment is performed on the oxide semiconductor surface, then the resistivity of exposed portions is reduced, but the source and drain regions are etched, decreasing their thickness
Solution Approach 1:
The patent applies preliminary action by forming highly doped regions in the oxide semiconductor layer before performing plasma treatment on the gate insulating film. The dopant is introduced into specific regions adjacent to the source and drain electrodes through ion implantation or diffusion, creating a dopant concentration distribution that reduces resistivity without requiring subsequent plasma treatment of the oxide semiconductor surface. This prevents etching damage to the source and drain regions while achieving the desired low-resistance contact.
3Reliability
If the oxide semiconductor layer thickness is increased to prevent etching, then the source and drain region resistance is reduced, but the channel thickness cannot be sufficiently reduced for short-channel effect prevention
Solution Approach 1:
The patent applies local quality by creating a vertical dopant concentration gradient within the oxide semiconductor layer. Highly doped regions are formed adjacent to the source and drain electrodes to reduce contact resistance, while the channel region maintains a thinner effective thickness and lower dopant concentration to prevent short-channel effects. This spatial differentiation allows the structure to simultaneously achieve low resistance and adequate channel control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses fluctuations in electric characteristics and enhances the reliability of the transistor by reducing resistance and preventing etching issues in thin oxide semiconductor layers, enabling successful miniaturization while maintaining functionality.
Implementation Method 1
a first doped region and a second doped region in an oxide semiconductor film, the first doped region and the second doped region being different from each other in dopant concentration
Data Source
AI summary
A semiconductor device in which fluctuation in electric characteristics due to miniaturization is less likely to be caused is provided. The semiconductor device includes an oxide semiconductor film including a first region, a pair of second regions in contact with side surfaces of the first region, and a pair of third regions in contact with side surfaces of the pair of second regions; a gate insulating film provided over the oxide semiconductor film; and a first electrode that is over the gate insulating film and overlaps with the first region. The first region is a CAAC oxide semiconductor region. The pair of second regions and the pair of third regions are each an amorphous oxide semiconductor region containing a dopant. The dopant concentration of the pair of third regions is higher than the dopant concentration of the pair of second regions.