CAAC-OS Transistor Contact Resistance via Hydrogen Plasma
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Solution Overview
Problem
Transistors manufactured using oxide semiconductors face challenges with short-channel effects and increased resistance due to argon plasma treatment, particularly when the channel length is less than 200 nm, leading to defective products and reduced on-state current.
Innovation Solution
A semiconductor device with a c-axis-aligned crystalline oxide semiconductor (CAAC-OS) film is used, where ions are added to form source and drain regions without overlapping with the gate electrode, reducing contact resistance and parasitic capacitance, and using an insulating film as a mask to protect the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If argon plasma treatment is performed on oxide semiconductor surfaces to decrease resistivity, then contact resistance is reduced, but the oxide semiconductor is etched off and thickness is reduced leading to increased resistance and defective products
Solution Approach 1:
The patent changes the atomic radius parameter of the plasma treatment ions from large (argon) to small (hydrogen, helium, neon). This parameter change allows plasma treatment to reduce resistivity without causing over-etching, as the smaller ions have less etching capability while still achieving the desired resistivity reduction in the oxide semiconductor.
Solution Approach 2:
The patent uses hydrogen plasma treatment as a temporary, controlled process to modify the oxide semiconductor surface properties. The hydrogen plasma is applied selectively to reduce resistivity in specific regions (source and drain regions) without permanently damaging the overall structure, allowing for controlled resistivity modification without long-term structural degradation.
2Length of moving object
If the channel length is reduced to less than 200 nm for device miniaturization, then device size is reduced, but short-channel effects increase and resistance increases
Solution Approach 1:
The patent applies different treatments to different regions of the oxide semiconductor. The source and drain regions receive hydrogen plasma treatment to reduce resistivity, while the channel region maintains its original properties. This local differentiation allows the channel to remain thin (less than 20 nm) for miniaturization while the source and drain regions have optimized conductivity, preventing short-channel effects.
Solution Approach 2:
The patent performs hydrogen plasma treatment on the oxide semiconductor before forming the gate electrode and other structures. This preliminary resistivity reduction in the source and drain regions ensures that when the device is miniaturized with short channel length, the contact resistance is already optimized, preventing the increase in overall resistance that would otherwise occur with shorter channels.
3Reliability
If the oxide semiconductor layer thickness is reduced to less than or equal to 20 nm to prevent short-channel effect, then short-channel effect is suppressed, but plasma treatment causes over-etching and increases resistance
Solution Approach 1:
The patent changes the plasma treatment parameters by using hydrogen ions instead of argon ions. This parameter change is critical because hydrogen ions have smaller atomic radius and lower etching capability, allowing plasma treatment to be performed on ultra-thin oxide semiconductor layers (less than 20 nm) without causing over-etching, while still achieving the desired resistivity reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes short-channel effects, enhances on-state current, and prevents over-etching, allowing for miniaturization of semiconductor devices while maintaining reliable electric characteristics.
Implementation Method 1
ions are added to form source and drain regions
Implementation Method 2
c-axis-aligned crystalline oxide semiconductor (CAAC-OS) film
Data Source
AI summary
A miniaturized semiconductor device including a transistor in which a channel formation region is formed using an oxide semiconductor film and variation in electric characteristics due to a short-channel effect is suppressed is provided. In addition, a semiconductor device whose on-state current is improved is provided. A semiconductor device is provided with an oxide semiconductor film including a pair of second oxide semiconductor regions which are amorphous regions and a first oxide semiconductor region located between the pair of second oxide semiconductor regions, a gate insulating film, and a gate electrode provided over the first oxide semiconductor region with the gate insulating film interposed therebetween. Hydrogen or a rare gas is added to the second oxide semiconductor regions.