Coherent Attached Bus RDMA Key-Value Store

The patent introduces a CAB (Coherent Accelerator Processor Interface) bus as an intermediary between RDMA adapters and shared memory. This CAB bus provides the memory pinning and registration functionality centrally, allowing multiple RDMA adapters to access the same memory regions without each adapter needing its own private registration. The CAB bus acts as the mediator that manages the coherence and access rights, reducing the complexity at each adapter while maintaining reliable access.

The patent implements a universal memory space that can be shared by multiple RDMA adapters through the CAB bus. Instead of each adapter having its own private registered memory regions, the system creates a universal shared memory space that all adapters can access. The CAB bus manages the security and coherence attributes, allowing the system to scale to many adapters while maintaining secure access control through a single unified interface.

The patent enables RDMA adapters to perform self-service memory access through the CAB bus without requiring CPU intervention for each access operation. The adapters can directly access the shared memory regions managed by the CAB bus, performing read and write operations autonomously. This self-service capability eliminates the need for CPU involvement in memory management and data transfer, thereby maximizing access bandwidth and productivity while the CAB bus maintains control precision through its coherence management.

The patent moves the storage capacity dimension from the accelerator card itself to the system's shared memory resources. Instead of being constrained by the limited onboard storage of FPGAs or other add-on accelerators, the system allows these high-speed processing units to access large容量的 shared memory through the CAB bus. This dimensional shift separates processing speed (provided by the accelerator) from storage capacity (provided by shared memory), allowing both to be optimized independently.