CABAC Context Encoding for Multi-Flag Processing Per Clock Cycle

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Solution Overview

Problem

The computational complexity of the CABAC encoding method in the H.264/AVC video coding standard hinders encoding and decoding speed, and conventional approaches to address this issue involve increasing operational frequency, which is undesirable.

Innovation Solution

A CABAC encoder comprising a reorganizing unit, context formation engines, and a CABAC coding engine that detects and processes coefficient flags to generate bins and context indices within a single clock cycle, optimizing the encoding process without increasing hardware frequency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If the CABAC encoding method is implemented with detailed context modeling and binary arithmetic coding, then compression efficiency is improved, but computational complexity increases and encoding speed is hindered

Engineering Contradiction:
Improvecompression efficiencyVSAvoidcomputational complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The encoding process is divided into distinct modules: reorganizing unit for input data arrangement, context formation engines for probability modeling, and CABAC coding engine for arithmetic encoding. This segmentation allows each module to be optimized independently while maintaining overall compression efficiency.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Coefficient flags are detected and organized in advance within the reorganizing unit before being processed by the context formation engines. This preliminary organization of data reduces the computational burden during the actual arithmetic encoding phase, improving overall encoding speed without sacrificing compression efficiency.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If hardware frequency is increased to handle computational complexity, then encoding speed is improved, but power consumption and operational complexity increase

Engineering Contradiction:
Improveencoding speedVSAvoidoperational frequency
Core Design Contradiction:
ProductivityVSPower

Solution Approach 1:

The encoder is divided into parallel processing units that can operate simultaneously at lower frequencies. The reorganizing unit prepares data while context formation engines build probability models, and the coding engine performs arithmetic encoding, allowing pipelined execution that maintains high throughput without requiring high operational frequency.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The context formation engines dynamically adapt probability models based on incoming data patterns, allowing the system to optimize processing speed for different video content types. This dynamic adaptation enables efficient encoding at variable rates without requiring consistently high operational frequency.

Inventive Principle:
Principle #15Dynamics

3Productivity

If multiple coefficient flags are processed per clock cycle, then encoding efficiency is improved, but circuit complexity increases

Engineering Contradiction:
Improveencoding efficiencyVSAvoidcircuit complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Multiple coefficient flags are detected and processed together in the reorganizing unit and context formation engines. By merging the detection and initial processing of multiple flags into unified circuit blocks, the patent achieves parallel processing of multiple coefficients per clock cycle while avoiding the need for separate dedicated circuits for each flag, thus improving encoding efficiency without proportionally increasing overall circuit complexity.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS8138956B2CABAC encoder and CABAC encoding method
Publication Date: 2012.03.20 MEDIATEK INC
  • US8138956B2 patent drawing
  • US8138956B2 patent drawing
  • US8138956B2 patent drawing

AI summary

A CABAC encoding method includes: receiving first and second coefficient flags (Sig, Last); detecting coefficient flags according to positions of the detected coefficient flags and control signal (Sig_first); generating first bin and second bin (bin_val_1, bin_val_2) corresponding to the detected coefficient flags according to the detecting result; updating a value of the second control signal (Sig_first) for the next clock cycle according to the detecting result; generating first and second position parameters (Sig/Last_pos_1, Sig/Last_pos_2) corresponding to the positions of the first and second bins (bin_val_1, bin_val_2); generating a first context index (Ctx_idx_1) according to the control signal (Sig_first) and the first position parameter (Sig/Last_pos_1) and a second context index (Ctx_idx_2) according to the control signal (Sig_first), the second position parameter (Sig/Last_pos_2) and the first bin (bin_val_1); and encoding the first and second bins (bin_val_1, bin_val_2) according to the first and second context indexes (Ctx_idx_1, Ctx_idx_2) respectively to generate the bit stream.