CABAC Entropy Encoder Normalization in a Single Clock Cycle
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Solution Overview
Problem
Existing CABAC encoding methods in FPGAs face bottlenecks due to inefficient normalization and renormalization processes, particularly in real-time encoding of HD sequences, which limit performance and efficiency.
Innovation Solution
An entropy encoder module is designed to perform normalization in a single clock cycle, utilizing a series of calculation blocks and registers to normalize and propagate LOW values efficiently, allowing for the output of an encoded bitstream while separating outstanding bit insertion from the normalization process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional normalization and renormalization processes are used in CABAC encoding, then encoding accuracy is maintained, but encoding speed and real-time performance deteriorate due to multiple clock cycles required
Solution Approach 1:
The patent divides the normalization process into multiple calculation blocks (first calculation block, second calculation block, third calculation block) that operate in parallel. Each block handles a specific portion of the normalization task, allowing simultaneous processing of different parts of the data, thereby reducing the total time required for normalization while maintaining encoding accuracy.
2Productivity
If multiple calculation blocks are used to perform normalization in parallel, then encoding efficiency is improved, but device complexity increases
Solution Approach 1:
The normalization function is segmented into three independent calculation blocks that can be implemented using standard logic circuit elements. This modular approach allows parallel processing while keeping each individual block relatively simple, balancing the trade-off between productivity and device complexity.
Solution Approach 2:
Registers are introduced as intermediary elements between the calculation blocks to store intermediate results. These registers act as buffers that facilitate data flow between blocks without requiring complex inter-block communication logic, thereby managing device complexity while enabling parallel operation.
3Speed
If normalization is performed completely within a single clock cycle, then real-time encoding capability is achieved, but the complexity of the normalization process increases
Solution Approach 1:
By dividing the normalization task across three calculation blocks that operate simultaneously within a single clock cycle, the patent achieves complete normalization in one cycle. The segmentation allows the complex task to be distributed, making the overall circuit complexity manageable through modular design.
Solution Approach 2:
The calculation blocks are pre-configured with the necessary logic to perform their specific normalization operations. This preliminary setup allows each block to execute its function immediately upon receiving input data, enabling complete normalization within a single clock cycle without requiring sequential processing steps.
Data Source
AI summary
An entropy encoder module (350) is configured to completely perform normalization of each binary input in a single clock cycle for Context Adaptive Binary Arithmetic Coding (CABAC). Outstanding bits are separated out from other bits of a portion of a frame for Context Adaptive Binary-Arithmetic Coding (CABAC). The outstanding bits are parsed responsive to location marking, counting, and bit masking to provide insert bits. The insert bits are inserted into the encoded bitstream for output. A Context Adaptive Binary Arithmetic Coding (“CABAC”) system includes: digital information storage (301) having digital video information stored therein; and a CABAC encoder (200) coupled to the digital information storage (301) to receive a portion of the digital video information at a time.