CABAC Entropy Decoding Vector Packing for Real-Time SIMD Processing

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Solution Overview

Problem

The decoding of high-definition AVC(H.264) streams using CABAC entropy decoding is computationally intensive and can become a bottleneck, preventing real-time decoding on general-purpose microprocessors like the Cell processor, due to its sequential nature which does not fully utilize the SIMD structure's parallel processing capabilities.

Innovation Solution

The implementation of a vector-type data packing scheme for entropy decoding, which packs codIRange, codIOffset, and input stream data into a single vector, allowing for fewer read operations and enabling SIMD processing to overcome the sequential bottlenecks in CABAC decoding, thereby improving processing efficiency and speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If CABAC entropy decoding is implemented on general-purpose microprocessors, then decoding capability is improved, but processing speed deteriorates due to sequential nature

Engineering Contradiction:
Improvedecoding capabilityVSAvoidprocessing speed
Core Design Contradiction:
Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent segments the entropy decoding process into independent parallel operations by organizing context models and probability states into separate vector elements that can be processed simultaneously using SIMD instructions, breaking the sequential dependency chain while maintaining decoding accuracy

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from scalar sequential processing to vector parallel processing by utilizing the SIMD structure's multiple data lanes, effectively adding a parallel processing dimension that allows simultaneous computation of multiple probability states and context updates

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Device complexity

If traditional scalar decoding methods are used, then implementation simplicity is maintained, but productivity deteriorates due to computational intensity

Engineering Contradiction:
Improveimplementation simplicityVSAvoiddecoding throughput
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent replaces the traditional scalar mechanical decoding process with vectorized SIMD operations, substituting the step-by-step scalar computation mechanism with a parallel vector processing mechanism that achieves higher throughput without proportionally increasing control complexity

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Speed

If SIMD processing is utilized, then processing speed is improved, but device complexity increases due to vector data packing requirements

Engineering Contradiction:
Improvedecoding speedVSAvoiddata packing complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent merges multiple decoding operations and data elements into unified vector structures, combining context states, probability values, and syntax element decodings into single vector operands that can be processed together, reducing the number of separate operations and memory accesses

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS8749409B2Entropy decoding methods and apparatus using most probable and least probable signal cases
Publication Date: 2014.06.10 SONY INTERACTIVE ENTERTAINMENT LLC
  • US8749409B2 patent drawing
  • US8749409B2 patent drawing
  • US8749409B2 patent drawing

AI summary

An entropy decoding apparatus may include a data structure stored in memory. The data structure may include a decoding engine vector or context engine vector. The decoding engine vector many have a first set of bits representing a value corresponding to a state of a coding engine, a second set of bits representing an offset value, and a third set of bits representing the contents of an input stream buffer. The context vector may have a first set of bits representing an addresses of a context most probable state, a second set of bits representing a plurality of possible values corresponding to a least probable symbol state of a coding engine, a third set of bits representing an addresses of a context least probable state, a fourth set of bits representing a binary most probable symbol value, and a fifth set of bits representing a binary least probable symbol value.