Selective Cache Access Control for Data Processor Power Optimization
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Solution Overview
Problem
Data processor units face performance and power consumption issues due to tight timing constraints in the access set-up cycle, where it may not be possible to definitively determine the memory location of instruction operands, leading to speculative cache access requests that reduce performance or increase power consumption.
Innovation Solution
A data processor unit that can definitively determine whether an effective address is within a local memory address range, preventing speculative cache access requests by comparing a base address value with the effective address input operands in parallel with calculating the access requests, thereby reducing unnecessary cache accesses and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple speculative access requests are generated to ensure instruction operand access, then performance is maintained, but power consumption increases
Solution Approach 1:
The patent applies local quality by differentiating between different types of memory access requests based on their certainty. Speculative access requests are generated only when necessary (when timing constraints prevent definitive determination), while definitive requests are used when possible. This selective approach optimizes the balance between performance and power consumption by applying different access strategies to different access scenarios.
Solution Approach 2:
The system dynamically adjusts its access strategy based on timing constraints and available information. The load/store unit can switch between generating multiple speculative requests, delaying requests, or using definitive single requests depending on whether the access set-up cycle allows for definitive determination. This dynamic adaptation resolves the contradiction by optimizing performance when possible and reducing power consumption when definitive determination is achievable.
2Measurement precision
If access request generation is delayed by a clock cycle to provide additional access set-up time, then definitive memory determination is possible, but performance reduces
Solution Approach 1:
The patent applies preliminary action by performing address calculation and memory determination as early as possible within the access set-up cycle. The system attempts to definitively determine the target memory during the set-up cycle itself, only delaying or speculating when absolutely necessary. This early determination approach minimizes performance impact while maximizing accuracy.
Solution Approach 2:
The system changes the timing parameter of access request generation based on whether definitive determination is possible. When timing constraints allow, requests are generated with full determination accuracy. When constraints prevent this, the system adjusts by either delaying by one clock cycle or generating speculative requests, changing the timing parameter to resolve the contradiction between accuracy and performance.
3Productivity
If a single speculative access request is generated to maintain performance, then performance is maintained, but the request may fail to access the instruction operand from the target device
Solution Approach 1:
The patent applies partial action by generating the minimum necessary number of access requests based on certainty levels. When definitive determination is possible, only one request is generated. When uncertain, multiple speculative requests are generated. This partial approach avoids excessive requests when not needed, resolving the contradiction by matching the number of requests to the actual uncertainty level.
Data Source
AI summary
A data processor is disclosed that definitively determines an effective address being calculated and decoded will be associated with an address range that includes a memory local to a data processor unit, and will disable a cache access based upon a comparison between a portion of a base address and a corresponding portion of an effective address input operand. Access to the local memory can be accomplished through a first port of the local memory when it is definitively determined that the effective address will be associated with an address range. Access to the local memory cannot be accomplished through the first port of the local memory when it is not definitively determined that the effective address will be associated with the address range.