Cache Memory Access Controller with Address Estimation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing cache memory technologies struggle to improve performance by efficiently determining cache hits and misses, leading to unnecessary access operations and performance degradation due to the inability to accurately predict next access addresses and optimize tag look-ahead operations.
Innovation Solution
A cache memory device that includes data memory and tag memory, with an address estimation unit to predict the next access address and a cache hit determination unit to retain the determination result, allowing the access controller to directly access the data memory or main memory based on the retained result, thereby eliminating unnecessary tag memory access and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If cache hit determination is performed using tag memory for every access, then cache hit/miss can be accurately determined, but unnecessary access operations occur and performance deteriorates
Solution Approach 1:
The patent performs cache hit determination in advance for addresses that are predicted to be accessed next. By determining cache hits before actual access occurs, the system can prepare the data path and avoid unnecessary tag memory access during the actual access operation, thus improving performance while maintaining determination accuracy
Solution Approach 2:
The system uses its own prediction capability to identify which addresses will be accessed next and performs cache hit determination only for those addresses. This self-directed approach eliminates the need for exhaustive tag memory access for all possible addresses, reducing unnecessary operations while maintaining accurate cache hit determination
2Reliability
If tag memory access is performed for every memory access, then cache hit determination can be completed, but access time increases and performance decreases
Solution Approach 1:
The patent performs cache hit determination in advance for predicted next addresses during idle periods or before actual access. This preliminary action allows the system to complete tag memory access before the actual data access is needed, eliminating the time penalty during critical access paths while maintaining complete and reliable cache hit determination
Solution Approach 2:
The system dynamically adjusts when tag memory access occurs based on predicted access patterns. Instead of static synchronous access for every memory operation, the system performs tag access asynchronously and selectively based on prediction, optimizing the timing of tag memory access to minimize impact on critical performance paths
3Ease of operation
If cache memory uses traditional access control, then simple operation is maintained, but performance optimization through prediction is limited
Solution Approach 1:
The patent introduces an address prediction unit as an intermediary between the memory access controller and tag memory. This intermediary component generates predicted addresses and triggers cache hit determination selectively, adding performance optimization capability while keeping the core cache control logic relatively simple and modular
Data Source
AI summary
A cache memory device includes: data memory that stores cache data corresponding to data in main memory; tag memory that stores tag information to identify the cache data; an address estimation unit that estimates a look-ahead address to be accessed next; a cache hit determination unit that performs cache hit determination on the look-ahead address, based on the stored tag information; and an access controller that accesses the data memory or the main memory based on the retained cache hit determination result in response to a next access.