Cache Access Circuitry Default Block Size Handling
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Solution Overview
Problem
In data processing systems, caches face complexity and performance issues when the size of address blocks is not initially indicated by the control device, leading to potential cache misses or unnecessary allocations, especially during reset events or when the actual size differs from the assumed default size.
Innovation Solution
The cache access circuitry assumes a default block size greater than the available sizes, allowing cache access requests to proceed and trigger refills, while updating the size indicator upon actual size indication from the control device, and includes an entry size indicator in each cache entry to determine the correct block size for searches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the cache access circuitry waits for the control device to indicate the block size before processing access requests, then the cache can use the correct block size for searches, but the system experiences increased latency and reduced performance
Solution Approach 1:
The cache access circuitry performs preliminary actions by assuming a default block size before the control device actually indicates the correct size. This allows cache access requests to proceed immediately without waiting for size indication, improving performance while maintaining correctness through subsequent size updates when the actual size is provided
2Productivity
If the cache access circuitry assumes a default block size smaller than the actual size, then cache access requests can proceed quickly, but the system experiences increased cache misses and unnecessary allocations
Solution Approach 1:
The system performs preliminary cache access operations using an assumed default block size to enable quick processing. When the control device subsequently indicates the actual block size, the cache access circuitry updates its size assumption, ensuring that subsequent operations use the correct size for accurate hit/miss determination
Solution Approach 2:
The control device provides feedback by indicating the actual block size to the cache access circuitry. This feedback mechanism allows the cache access circuitry to correct its initial assumptions about block size, ensuring accurate cache operation while maintaining high performance through the preliminary assumption phase
3Quantity of substance
If the cache access circuitry assumes a default block size larger than the actual size, then unnecessary cache allocations are reduced, but the system may experience increased memory usage and potential cache blockage
Solution Approach 1:
The cache access circuitry assumes a default block size larger than some available sizes as a preliminary measure. This assumption reduces unnecessary cache allocations during the initial phase. When the control device indicates the actual block size, the circuitry updates its assumption, preventing cache blockage while maintaining allocation efficiency
4Adaptability or versatility
If the cache access circuitry uses multiple block size indicators and updates them dynamically, then the system achieves flexibility and correctness, but the device complexity increases
Solution Approach 1:
The cache access circuitry maintains a first block size indicator with a default value as a preliminary measure. When the control device provides the actual block size indication, a second block size indicator is updated. This two-indicator approach provides flexibility and correctness while managing complexity through a structured update mechanism
Data Source
AI summary
An apparatus has a cache configured to store entries which correspond to blocks of addresses having one of a plurality of sizes as selected by a control device. When the control device has not yet indicated which size to use, cache access circuitry assumes a default size which is greater than at least one of the plurality of sizes.