Cache Access Delay Reduction via Pre-fetch Mechanism
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Solution Overview
Problem
The multi-level cache architecture, while improving access performance, introduces delays and redundant power consumption due to level-by-level access, especially when there are misses and low hit rates.
Innovation Solution
A method and device for accessing cache that reads an access instruction, determines if a delay is produced using a delay identifier, performs a pre-fetch operation based on a location identifier if a delay is detected, and modifies the identifiers based on the data's location, optimizing cache access by predicting and reducing delays and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a multi-level cache architecture is introduced to improve access performance, then the access speed is improved, but the access delay increases due to level-by-level access
Solution Approach 1:
The patent introduces a pre-fetch mechanism that proactively loads data into the cache before it is actually needed by the processor. By predicting future memory access patterns and pre-loading data into appropriate cache levels, the system eliminates the need for sequential level-by-level access when data is requested, thereby reducing access delay while maintaining the multi-level cache architecture's speed benefits
2Loss of time
If level-by-level access to each level of cache is performed, then the access delay is reduced, but redundant power consumption is generated
Solution Approach 1:
The pre-fetch mechanism loads data into the cache hierarchy in advance, so when the processor needs the data, it is already available in the cache without requiring sequential access through multiple cache levels. This eliminates redundant access operations to lower cache levels, thereby reducing power consumption while maintaining fast access performance
Solution Approach 2:
The patent extracts and eliminates redundant cache access operations by using the pre-fetch mechanism to directly load data into the appropriate cache level. By removing the unnecessary intermediate access steps through multiple cache levels, the system reduces power consumption associated with these redundant access operations
3Reliability
If simultaneously accessing each level of cache is performed to improve hit rate, then the miss rate is reduced, but more redundant power consumption is generated
Solution Approach 1:
Instead of simultaneously accessing all cache levels, the pre-fetch mechanism proactively loads data into the cache hierarchy before it is needed. This ensures high hit rates by having data ready in advance, while avoiding the power consumption of simultaneous multi-level access operations since only the necessary cache levels are accessed
Data Source
AI summary
A method for accessing a cache including reading an access instruction for acquiring data; determining, according to a delay identifier carried by the access instruction, whether the access instruction produces a delay; accessing the cache and performing, according to a location identifier carried by the access instruction, a pre-fetch operation if a delay is produced; and modifying, according to a location where the data required by the access instruction is acquired, the delay identifier and the location identifier carried by the access instruction. The technical solutions solve the problem of a low hit rate upon cache access, reduce the probability of misses, and reduce an access delay caused by a level-by-level access to each level of cache upon target data acquisition, which correspondingly lowers the power consumption generated upon the cache access and improves the CPU performance.